2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2014-12-12 13:05:25 +00:00
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/*
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* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
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*
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* Adapted from coreboot src/include/device/pnp_def.h
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* and arch/x86/include/arch/io.h
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*/
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#ifndef _ASM_PNP_DEF_H_
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#define _ASM_PNP_DEF_H_
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#include <asm/io.h>
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#define PNP_IDX_EN 0x30
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#define PNP_IDX_IO0 0x60
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#define PNP_IDX_IO1 0x62
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#define PNP_IDX_IO2 0x64
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#define PNP_IDX_IO3 0x66
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#define PNP_IDX_IRQ0 0x70
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#define PNP_IDX_IRQ1 0x72
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#define PNP_IDX_DRQ0 0x74
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#define PNP_IDX_DRQ1 0x75
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#define PNP_IDX_MSC0 0xf0
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#define PNP_IDX_MSC1 0xf1
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/* Generic functions for pnp devices */
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/*
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* pnp device is a 16-bit integer composed of its i/o port address at high byte
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* and logic function number at low byte.
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*/
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#define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC))
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static inline void pnp_write_config(uint16_t dev, uint8_t reg, uint8_t value)
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{
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uint8_t port = dev >> 8;
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outb(reg, port);
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outb(value, port + 1);
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}
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static inline uint8_t pnp_read_config(uint16_t dev, uint8_t reg)
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{
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uint8_t port = dev >> 8;
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outb(reg, port);
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return inb(port + 1);
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}
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static inline void pnp_set_logical_device(uint16_t dev)
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{
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uint8_t device = dev & 0xff;
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pnp_write_config(dev, 0x07, device);
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}
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static inline void pnp_set_enable(uint16_t dev, int enable)
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{
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pnp_write_config(dev, PNP_IDX_EN, enable ? 1 : 0);
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}
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static inline int pnp_read_enable(uint16_t dev)
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{
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return !!pnp_read_config(dev, PNP_IDX_EN);
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}
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static inline void pnp_set_iobase(uint16_t dev, uint8_t index, uint16_t iobase)
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{
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pnp_write_config(dev, index + 0, (iobase >> 8) & 0xff);
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pnp_write_config(dev, index + 1, iobase & 0xff);
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}
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static inline uint16_t pnp_read_iobase(uint16_t dev, uint8_t index)
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{
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return ((uint16_t)(pnp_read_config(dev, index)) << 8) |
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pnp_read_config(dev, index + 1);
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}
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static inline void pnp_set_irq(uint16_t dev, uint8_t index, unsigned irq)
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{
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pnp_write_config(dev, index, irq);
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}
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static inline void pnp_set_drq(uint16_t dev, uint8_t index, unsigned drq)
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{
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pnp_write_config(dev, index, drq & 0xff);
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}
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#endif /* _ASM_PNP_DEF_H_ */
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