Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-16 17:58:23 +00:00
Code Issues Projects Releases Packages Wiki Activity
u-boot/include/configs/synquacer.h

104 lines
2.5 KiB
C
Raw Normal View History

board: synquacer: Add DeveloperBox 96boards EE support Add the DeveloperBox 96boards EE support. This board is also known as Socionext SynQuacer E-Series. It contians one "SC2A11" SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots, 3 PCIe slots (1 4x port and 2 1x ports which are expanded via PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard MicroATX Form Factor. For more information, see this page; https://www.96boards.org/product/developerbox/ Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-06-04 09:45:10 +00:00
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2016-2017 Socionext Inc.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* Timers for fasp(TIMCLK) */
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:41 +00:00
#define CFG_SYS_TIMERBASE 0x31080000 /* AP Timer 1 (ARM-SP804) */
board: synquacer: Add DeveloperBox 96boards EE support Add the DeveloperBox 96boards EE support. This board is also known as Socionext SynQuacer E-Series. It contians one "SC2A11" SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots, 3 PCIe slots (1 4x port and 2 1x ports which are expanded via PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard MicroATX Form Factor. For more information, see this page; https://www.96boards.org/product/developerbox/ Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-06-04 09:45:10 +00:00
/*
* SDRAM (for initialize)
*/
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:37 +00:00
#define CFG_SYS_SDRAM_BASE (0x80000000) /* Start address of DDR3 */
board: synquacer: Add DeveloperBox 96boards EE support Add the DeveloperBox 96boards EE support. This board is also known as Socionext SynQuacer E-Series. It contians one "SC2A11" SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots, 3 PCIe slots (1 4x port and 2 1x ports which are expanded via PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard MicroATX Form Factor. For more information, see this page; https://www.96boards.org/product/developerbox/ Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-06-04 09:45:10 +00:00
#define PHYS_SDRAM_SIZE (0x7c000000) /* Default size (2GB - Secure memory) */
global: Migrate CONFIG_MAX_MEM_MAPPED to CFG Perform a simple rename of CONFIG_MAX_MEM_MAPPED to CFG_MAX_MEM_MAPPED Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-04 15:04:50 +00:00
#define CFG_MAX_MEM_MAPPED PHYS_SDRAM_SIZE
board: synquacer: Add DeveloperBox 96boards EE support Add the DeveloperBox 96boards EE support. This board is also known as Socionext SynQuacer E-Series. It contians one "SC2A11" SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots, 3 PCIe slots (1 4x port and 2 1x ports which are expanded via PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard MicroATX Form Factor. For more information, see this page; https://www.96boards.org/product/developerbox/ Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-06-04 09:45:10 +00:00
#define SQ_DRAMINFO_BASE (0x2e00ffc0) /* DRAM info from TF-A */
/*
* Boot info
*/
/*
* Hardware drivers support
*/
/* RTC */
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:41 +00:00
#define CFG_SYS_I2C_RTC_ADDR 0x51
board: synquacer: Add DeveloperBox 96boards EE support Add the DeveloperBox 96boards EE support. This board is also known as Socionext SynQuacer E-Series. It contians one "SC2A11" SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots, 3 PCIe slots (1 4x port and 2 1x ports which are expanded via PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard MicroATX Form Factor. For more information, see this page; https://www.96boards.org/product/developerbox/ Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-06-04 09:45:10 +00:00
/* Serial (pl011) */
#define UART_CLK (62500000)
#define CONFIG_PL011_CLOCK UART_CLK
#define CONFIG_PL01x_PORTS {(void *)(0x2a400000)}
/* Support MTD */
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:41 +00:00
#define CFG_SYS_FLASH_BASE (0x08000000)
#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE}
board: synquacer: Add DeveloperBox 96boards EE support Add the DeveloperBox 96boards EE support. This board is also known as Socionext SynQuacer E-Series. It contians one "SC2A11" SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots, 3 PCIe slots (1 4x port and 2 1x ports which are expanded via PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard MicroATX Form Factor. For more information, see this page; https://www.96boards.org/product/developerbox/ Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-06-04 09:45:10 +00:00
/* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */
configs: synquacer: Enable EFI capsule update support Enable EFI capsule update support. With the EFI capsule update, you can update U-Boot, TF-A and OP-TEE. TF-A and OP-TEE are usually combined as a FIP binary, but if the binary is bigger than 480KB, you have to modify FIP header, split the OP-TEE and stores the OP-TEE binary in the different place. This configuration supports both cases. Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-06-04 09:45:31 +00:00
#define DEFAULT_DFU_ALT_INFO "dfu_alt_info=" \
configs: synquacer: Fix dfu_alt_info to use nor1 Fix dfu_alt_info to use nor1 instead of the device name. This reverts a part of commit 59bd18d4c4d7 ("configs: synquacer: Remove mtdparts settings and update DFU setting") because the commit a4f2d8341455 ("mtd: spi: nor: force mtd name to "nor%d"") changed the mtd device naming scheme to nor%d. Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org> Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2021-11-10 00:40:07 +00:00
"mtd nor1=u-boot.bin raw 200000 100000;" \
configs: synquacer: Enable EFI capsule update support Enable EFI capsule update support. With the EFI capsule update, you can update U-Boot, TF-A and OP-TEE. TF-A and OP-TEE are usually combined as a FIP binary, but if the binary is bigger than 480KB, you have to modify FIP header, split the OP-TEE and stores the OP-TEE binary in the different place. This configuration supports both cases. Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-06-04 09:45:31 +00:00
"fip.bin raw 180000 78000;" \
"optee.bin raw 500000 100000\0"
capsule: board: Add information needed for capsule updates Add a structure which defines the information that is needed for executing capsule updates on a platform. Some information in the structure like the dfu string is used for making the update process more robust while some information like the per platform image GUIDs is used for fixing issues. Initialise this structure in the board file, and use the information for the capsule updates. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
2022-04-15 05:59:34 +00:00
/* GUIDs for capsule updatable firmware images */
#define DEVELOPERBOX_UBOOT_IMAGE_GUID \
EFI_GUID(0x53a92e83, 0x4ef4, 0x473a, 0x8b, 0x0d, \
0xb5, 0xd8, 0xc7, 0xb2, 0xd6, 0x00)
#define DEVELOPERBOX_FIP_IMAGE_GUID \
EFI_GUID(0x880866e9, 0x84ba, 0x4793, 0xa9, 0x08, \
0x33, 0xe0, 0xb9, 0x16, 0xf3, 0x98)
#define DEVELOPERBOX_OPTEE_IMAGE_GUID \
EFI_GUID(0xc1b629f1, 0xce0e, 0x4894, 0x82, 0xbf, \
0xf0, 0xa3, 0x83, 0x87, 0xe6, 0x30)
board: synquacer: Add DeveloperBox 96boards EE support Add the DeveloperBox 96boards EE support. This board is also known as Socionext SynQuacer E-Series. It contians one "SC2A11" SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots, 3 PCIe slots (1 4x port and 2 1x ports which are expanded via PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard MicroATX Form Factor. For more information, see this page; https://www.96boards.org/product/developerbox/ Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-06-04 09:45:10 +00:00
/* Distro boot settings */
#ifdef CONFIG_CMD_USB
#define BOOT_TARGET_DEVICE_USB(func) func(USB, usb, 0)
#else
#define BOOT_TARGET_DEVICE_USB(func)
#endif
#ifdef CONFIG_CMD_MMC
#define BOOT_TARGET_DEVICE_MMC(func) func(MMC, mmc, 0)
#else
#define BOOT_TARGET_DEVICE_MMC(func)
#endif
#ifdef CONFIG_CMD_NVME
#define BOOT_TARGET_DEVICE_NVME(func) func(NVME, nvme, 0)
#else
#define BOOT_TARGET_DEVICE_NVME(func)
#endif
#ifdef CONFIG_CMD_SCSI
#define BOOT_TARGET_DEVICE_SCSI(func) func(SCSI, scsi, 0) func(SCSI, scsi, 1)
#else
#define BOOT_TARGET_DEVICE_SCSI(func)
#endif
#define BOOT_TARGET_DEVICES(func) \
BOOT_TARGET_DEVICE_USB(func) \
BOOT_TARGET_DEVICE_MMC(func) \
BOOT_TARGET_DEVICE_SCSI(func) \
BOOT_TARGET_DEVICE_NVME(func) \
#include <config_distro_bootcmd.h>
global: Migrate CONFIG_EXTRA_ENV_SETTINGS to CFG Perform a simple rename of CONFIG_EXTRA_ENV_SETTINGS to CFG_EXTRA_ENV_SETTINGS Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-04 15:03:50 +00:00
#define CFG_EXTRA_ENV_SETTINGS \
board: synquacer: Add DeveloperBox 96boards EE support Add the DeveloperBox 96boards EE support. This board is also known as Socionext SynQuacer E-Series. It contians one "SC2A11" SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots, 3 PCIe slots (1 4x port and 2 1x ports which are expanded via PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard MicroATX Form Factor. For more information, see this page; https://www.96boards.org/product/developerbox/ Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-06-04 09:45:10 +00:00
"fdt_addr_r=0x9fe00000\0" \
"kernel_addr_r=0x90000000\0" \
"ramdisk_addr_r=0xa0000000\0" \
"scriptaddr=0x88000000\0" \
"pxefile_addr_r=0x88100000\0" \
configs: synquacer: Enable EFI capsule update support Enable EFI capsule update support. With the EFI capsule update, you can update U-Boot, TF-A and OP-TEE. TF-A and OP-TEE are usually combined as a FIP binary, but if the binary is bigger than 480KB, you have to modify FIP header, split the OP-TEE and stores the OP-TEE binary in the different place. This configuration supports both cases. Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-06-04 09:45:31 +00:00
DEFAULT_DFU_ALT_INFO \
board: synquacer: Add DeveloperBox 96boards EE support Add the DeveloperBox 96boards EE support. This board is also known as Socionext SynQuacer E-Series. It contians one "SC2A11" SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots, 3 PCIe slots (1 4x port and 2 1x ports which are expanded via PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard MicroATX Form Factor. For more information, see this page; https://www.96boards.org/product/developerbox/ Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-06-04 09:45:10 +00:00
BOOTENV
#endif /* __CONFIG_H */
Reference in a new issue Copy permalink