mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-21 02:33:07 +00:00
162 lines
3 KiB
ArmAsm
162 lines
3 KiB
ArmAsm
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2022 MediaTek Inc. All rights reserved.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <asm/asm.h>
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#include <asm/regdef.h>
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#include <asm/addrspace.h>
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#include <asm/mipsregs.h>
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#include <asm/cm.h>
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#include "../mt7621.h"
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#define SP_ADDR_TEMP 0xbe10dff0
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.set noreorder
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.macro init_wr sel
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MTC0 zero, CP0_WATCHLO,\sel
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mtc0 t1, CP0_WATCHHI,\sel
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.endm
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.macro uhi_mips_exception
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move k0, t9 # preserve t9 in k0
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move k1, a0 # preserve a0 in k1
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li t9, 15 # UHI exception operation
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li a0, 0 # Use hard register context
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sdbbp 1 # Invoke UHI operation
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.endm
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ENTRY(_start)
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b reset
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mtc0 zero, CP0_COUNT
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/*
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* Store TPL size here.
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* This will be used by SPL to locate u-boot payload.
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*/
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.org TPL_INFO_OFFSET
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.word TPL_INFO_MAGIC
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.word __image_copy_len
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/* Exception vector */
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.org 0x200
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/* TLB refill, 32 bit task */
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uhi_mips_exception
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.org 0x280
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/* XTLB refill, 64 bit task */
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uhi_mips_exception
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.org 0x300
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/* Cache error exception */
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uhi_mips_exception
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.org 0x380
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/* General exception */
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uhi_mips_exception
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.org 0x400
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/* Catch interrupt exceptions */
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uhi_mips_exception
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.org 0x480
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/* EJTAG debug exception */
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1: b 1b
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nop
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.org 0x500
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reset:
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/* Set KSEG0 to Uncached */
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mfc0 t0, CP0_CONFIG
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ins t0, zero, 0, 3
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ori t0, t0, CONF_CM_UNCACHED
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mtc0 t0, CP0_CONFIG
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ehb
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/* Check for CPU number */
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mfc0 t0, CP0_EBASE
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and t0, t0, MIPS_EBASE_CPUNUM
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beqz t0, 1f
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nop
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/* Secondary core goes to specified SPL entry address */
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li t0, KSEG1ADDR(SYSCTL_BASE)
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lw t0, BOOT_SRAM_BASE_REG(t0)
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jr t0
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nop
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/* Init CP0 Status */
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1: mfc0 t0, CP0_STATUS
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and t0, ST0_IMPL
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or t0, ST0_BEV | ST0_ERL
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mtc0 t0, CP0_STATUS
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nop
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/* Clear Watch Status bits and disable watch exceptions */
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li t1, 0x7 # Clear I, R and W conditions
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init_wr 0
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init_wr 1
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init_wr 2
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init_wr 3
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/* Clear WP, IV and SW interrupts */
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mtc0 zero, CP0_CAUSE
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/* Clear timer interrupt (CP0_COUNT cleared on branch to 'reset') */
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mtc0 zero, CP0_COMPARE
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/* Setup basic CPS */
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bal mips_cm_map
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nop
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li t0, KSEG1ADDR(CONFIG_MIPS_CM_BASE)
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li t1, GCR_REG0_BASE_VALUE
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sw t1, GCR_REG0_BASE(t0)
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li t1, ((GCR_REG0_MASK_VALUE << GCR_REGn_MASK_ADDRMASK_SHIFT) | \
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GCR_REGn_MASK_CMTGT_IOCU0)
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sw t1, GCR_REG0_MASK(t0)
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lw t1, GCR_BASE(t0)
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ins t1, zero, 0, 2 # CM_DEFAULT_TARGET
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sw t1, GCR_BASE(t0)
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lw t1, GCR_CONTROL(t0)
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li t2, GCR_CONTROL_SYNCCTL
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or t1, t1, t2
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sw t1, GCR_CONTROL(t0)
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/* Increase SPI frequency */
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li t0, KSEG1ADDR(SPI_BASE)
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li t1, 5
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sw t1, SPI_SPACE_REG(t0)
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/* Set CPU clock to 500MHz */
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li t0, KSEG1ADDR(SYSCTL_BASE)
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lw t1, SYSCTL_CLKCFG0_REG(t0)
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ins t1, zero, 30, 2 # CPU_CLK_SEL
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sw t1, SYSCTL_CLKCFG0_REG(t0)
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/* Set CPU clock divider to 1/1 */
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li t0, KSEG1ADDR(RBUS_BASE)
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li t1, 0x101
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sw t1, RBUS_DYN_CFG0_REG(t0)
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/* Initialize the SRAM */
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bal mips_sram_init
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nop
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/* Set up initial stack */
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li sp, SP_ADDR_TEMP
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bal tpl_main
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nop
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END(_start)
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