2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2018-03-08 10:00:27 +00:00
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/*
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* Copyright 2015-2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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*/
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#ifndef _CBUS_H_
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#define _CBUS_H_
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#include "cbus/emac.h"
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#include "cbus/gpi.h"
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#include "cbus/bmu.h"
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#include "cbus/hif.h"
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#include "cbus/tmu_csr.h"
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#include "cbus/class_csr.h"
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#include "cbus/hif_nocpy.h"
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#include "cbus/util_csr.h"
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#define CBUS_BASE_ADDR ((void *)CONFIG_SYS_FSL_PFE_ADDR)
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/* PFE Control and Status Register Desciption */
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#define EMAC1_BASE_ADDR (CBUS_BASE_ADDR + 0x200000)
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#define EGPI1_BASE_ADDR (CBUS_BASE_ADDR + 0x210000)
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#define EMAC2_BASE_ADDR (CBUS_BASE_ADDR + 0x220000)
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#define EGPI2_BASE_ADDR (CBUS_BASE_ADDR + 0x230000)
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#define BMU1_BASE_ADDR (CBUS_BASE_ADDR + 0x240000)
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#define BMU2_BASE_ADDR (CBUS_BASE_ADDR + 0x250000)
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#define ARB_BASE_ADDR (CBUS_BASE_ADDR + 0x260000)
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#define DDR_CONFIG_BASE_ADDR (CBUS_BASE_ADDR + 0x270000)
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#define HIF_BASE_ADDR (CBUS_BASE_ADDR + 0x280000)
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#define HGPI_BASE_ADDR (CBUS_BASE_ADDR + 0x290000)
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#define LMEM_BASE_ADDR (CBUS_BASE_ADDR + 0x300000)
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#define LMEM_SIZE 0x10000
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#define LMEM_END (LMEM_BASE_ADDR + LMEM_SIZE)
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#define TMU_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x310000)
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#define CLASS_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x320000)
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#define HIF_NOCPY_BASE_ADDR (CBUS_BASE_ADDR + 0x350000)
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#define UTIL_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x360000)
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#define CBUS_GPT_BASE_ADDR (CBUS_BASE_ADDR + 0x370000)
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/*
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* defgroup XXX_MEM_ACCESS_ADDR PE memory access through CSR
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* XXX_MEM_ACCESS_ADDR register bit definitions.
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*/
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/* Internal Memory Write. */
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#define PE_MEM_ACCESS_WRITE BIT(31)
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/* Internal Memory Read. */
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#define PE_MEM_ACCESS_READ (0 << 31)
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#define PE_MEM_ACCESS_IMEM BIT(15)
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#define PE_MEM_ACCESS_DMEM BIT(16)
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/* Byte Enables of the Internal memory access. These are interpred in BE */
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#define PE_MEM_ACCESS_BYTE_ENABLE(offset, size) (((((1 << (size)) - 1) << (4 \
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- (offset) - (size)))\
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& 0xf) << 24)
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/* PFE cores states */
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#define CORE_DISABLE 0x00000000
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#define CORE_ENABLE 0x00000001
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#define CORE_SW_RESET 0x00000002
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/* LMEM defines */
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#define LMEM_HDR_SIZE 0x0010
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#define LMEM_BUF_SIZE_LN2 0x7
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#define LMEM_BUF_SIZE BIT(LMEM_BUF_SIZE_LN2)
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/* DDR defines */
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#define DDR_HDR_SIZE 0x0100
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#define DDR_BUF_SIZE_LN2 0xb
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#define DDR_BUF_SIZE BIT(DDR_BUF_SIZE_LN2)
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/* Clock generation through PLL */
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#define PLL_CLK_EN 1
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#endif /* _CBUS_H_ */
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