2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2012-02-23 03:28:41 +00:00
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/*
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* Copyright (c) 2004-2008 Texas Instruments
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*
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* (C) Copyright 2002
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* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
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*/
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2014-07-12 13:24:02 +00:00
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#include <config.h>
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2016-06-19 04:38:36 +00:00
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#include <asm/psci.h>
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2014-07-12 13:24:02 +00:00
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2012-02-23 03:28:41 +00:00
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OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
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OUTPUT_ARCH(arm)
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ENTRY(_start)
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SECTIONS
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{
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2016-03-14 01:07:29 +00:00
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#ifndef CONFIG_CMDLINE
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2022-05-30 10:00:04 +00:00
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/DISCARD/ : { *(__u_boot_list_2_cmd_*) }
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2016-03-14 01:07:29 +00:00
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#endif
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ARM: Disable "DISCARD" for secure section if CONFIG_ARMV7_SECURE_BASE isn't defined
"DISCARD" will remove ._secure.text relocate, but PSCI framework
has already used some absolute address those need to relocate.
Use readelf -t -r u-boot show us:
.__secure_start addr: 601408e4
.__secure_end addr: 60141460
60141140 00000017 R_ARM_RELATIVE
46 _secure_monitor:
47 #ifdef CONFIG_ARMV7_PSCI
48 ldr r5, =_psci_vectors
60141194 00000017 R_ARM_RELATIVE
6014119c 00000017 R_ARM_RELATIVE
601411a4 00000017 R_ARM_RELATIVE
601411ac 00000017 R_ARM_RELATIVE
64 _psci_table:
66 .word psci_cpu_suspend
...
72 .word psci_migrate
60141344 00000017 R_ARM_RELATIVE
6014145c 00000017 R_ARM_RELATIVE
202 ldr r5, =psci_text_end
Solutions:
1. Change absolute address to RelAdr.
Based on LDR (immediate, ARM), we only have 4K offset to jump.
Now PSCI code size is close to 4K size that is LDR limit jump size,
so even if the LDR is based on the current instruction address,
there is also have a risk for RelAdr. If we use two jump steps I
think we can fix this issue, but looks too hack, so give up this way.
2. Enable "DISCARD" only for CONFIG_ARMV7_SECURE_BASE has defined.
If CONFIG_ARMV7_SECURE_BASE is defined in platform, all of secure
will in the BASE address that is absolute.
Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-18 03:02:40 +00:00
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#if defined(CONFIG_ARMV7_SECURE_BASE) && defined(CONFIG_ARMV7_NONSEC)
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arm: discard relocation entries for secure text
The code such as PSCI in section named secure is bundled with
u-boot image, and when bootm, the code will be copied to their
runtime address same to compliation/linking address -
CONFIG_ARMV7_SECURE_BASE.
When compile the PSCI code and link it into the u-boot image,
there will be relocation entries in .rel.dyn section for PSCI.
Actually, we do not needs these relocation entries.
If still keep the relocation entries in .rel.dyn section,
r0 at line 103 and 106 in arch/arm/lib/relocate.S may be an invalid
address which may not support read/write for one SoC.
102 /* relative fix: increase location by offset */
103 add r0, r0, r4
104 ldr r1, [r0]
105 add r1, r1, r4
106 str r1, [r0]
So discard them to avoid touching the relocation entry in
arch/arm/lib/relocate.S.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Tom Warren <twarren@nvidia.com>
Cc: York Sun <yorksun@freescale.com>
Cc: Hans De Goede <hdegoede@redhat.com>
Cc: Ian Campbell <ijc@hellion.org.uk>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@konsulko.com>
Cc: Jan Kiszka <jan.kiszka@siemens.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2015-10-23 02:13:03 +00:00
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/*
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ARM: Disable "DISCARD" for secure section if CONFIG_ARMV7_SECURE_BASE isn't defined
"DISCARD" will remove ._secure.text relocate, but PSCI framework
has already used some absolute address those need to relocate.
Use readelf -t -r u-boot show us:
.__secure_start addr: 601408e4
.__secure_end addr: 60141460
60141140 00000017 R_ARM_RELATIVE
46 _secure_monitor:
47 #ifdef CONFIG_ARMV7_PSCI
48 ldr r5, =_psci_vectors
60141194 00000017 R_ARM_RELATIVE
6014119c 00000017 R_ARM_RELATIVE
601411a4 00000017 R_ARM_RELATIVE
601411ac 00000017 R_ARM_RELATIVE
64 _psci_table:
66 .word psci_cpu_suspend
...
72 .word psci_migrate
60141344 00000017 R_ARM_RELATIVE
6014145c 00000017 R_ARM_RELATIVE
202 ldr r5, =psci_text_end
Solutions:
1. Change absolute address to RelAdr.
Based on LDR (immediate, ARM), we only have 4K offset to jump.
Now PSCI code size is close to 4K size that is LDR limit jump size,
so even if the LDR is based on the current instruction address,
there is also have a risk for RelAdr. If we use two jump steps I
think we can fix this issue, but looks too hack, so give up this way.
2. Enable "DISCARD" only for CONFIG_ARMV7_SECURE_BASE has defined.
If CONFIG_ARMV7_SECURE_BASE is defined in platform, all of secure
will in the BASE address that is absolute.
Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-18 03:02:40 +00:00
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* If CONFIG_ARMV7_SECURE_BASE is true, secure code will not
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* bundle with u-boot, and code offsets are fixed. Secure zone
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* only needs to be copied from the loading address to
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* CONFIG_ARMV7_SECURE_BASE, which is the linking and running
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* address for secure code.
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arm: discard relocation entries for secure text
The code such as PSCI in section named secure is bundled with
u-boot image, and when bootm, the code will be copied to their
runtime address same to compliation/linking address -
CONFIG_ARMV7_SECURE_BASE.
When compile the PSCI code and link it into the u-boot image,
there will be relocation entries in .rel.dyn section for PSCI.
Actually, we do not needs these relocation entries.
If still keep the relocation entries in .rel.dyn section,
r0 at line 103 and 106 in arch/arm/lib/relocate.S may be an invalid
address which may not support read/write for one SoC.
102 /* relative fix: increase location by offset */
103 add r0, r0, r4
104 ldr r1, [r0]
105 add r1, r1, r4
106 str r1, [r0]
So discard them to avoid touching the relocation entry in
arch/arm/lib/relocate.S.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Tom Warren <twarren@nvidia.com>
Cc: York Sun <yorksun@freescale.com>
Cc: Hans De Goede <hdegoede@redhat.com>
Cc: Ian Campbell <ijc@hellion.org.uk>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@konsulko.com>
Cc: Jan Kiszka <jan.kiszka@siemens.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2015-10-23 02:13:03 +00:00
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*
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ARM: Disable "DISCARD" for secure section if CONFIG_ARMV7_SECURE_BASE isn't defined
"DISCARD" will remove ._secure.text relocate, but PSCI framework
has already used some absolute address those need to relocate.
Use readelf -t -r u-boot show us:
.__secure_start addr: 601408e4
.__secure_end addr: 60141460
60141140 00000017 R_ARM_RELATIVE
46 _secure_monitor:
47 #ifdef CONFIG_ARMV7_PSCI
48 ldr r5, =_psci_vectors
60141194 00000017 R_ARM_RELATIVE
6014119c 00000017 R_ARM_RELATIVE
601411a4 00000017 R_ARM_RELATIVE
601411ac 00000017 R_ARM_RELATIVE
64 _psci_table:
66 .word psci_cpu_suspend
...
72 .word psci_migrate
60141344 00000017 R_ARM_RELATIVE
6014145c 00000017 R_ARM_RELATIVE
202 ldr r5, =psci_text_end
Solutions:
1. Change absolute address to RelAdr.
Based on LDR (immediate, ARM), we only have 4K offset to jump.
Now PSCI code size is close to 4K size that is LDR limit jump size,
so even if the LDR is based on the current instruction address,
there is also have a risk for RelAdr. If we use two jump steps I
think we can fix this issue, but looks too hack, so give up this way.
2. Enable "DISCARD" only for CONFIG_ARMV7_SECURE_BASE has defined.
If CONFIG_ARMV7_SECURE_BASE is defined in platform, all of secure
will in the BASE address that is absolute.
Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-18 03:02:40 +00:00
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* If CONFIG_ARMV7_SECURE_BASE is undefined, the secure zone will
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* be included in u-boot address space, and some absolute address
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* were used in secure code. The absolute addresses of the secure
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* code also needs to be relocated along with the accompanying u-boot
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* code.
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*
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* So DISCARD is only for CONFIG_ARMV7_SECURE_BASE.
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arm: discard relocation entries for secure text
The code such as PSCI in section named secure is bundled with
u-boot image, and when bootm, the code will be copied to their
runtime address same to compliation/linking address -
CONFIG_ARMV7_SECURE_BASE.
When compile the PSCI code and link it into the u-boot image,
there will be relocation entries in .rel.dyn section for PSCI.
Actually, we do not needs these relocation entries.
If still keep the relocation entries in .rel.dyn section,
r0 at line 103 and 106 in arch/arm/lib/relocate.S may be an invalid
address which may not support read/write for one SoC.
102 /* relative fix: increase location by offset */
103 add r0, r0, r4
104 ldr r1, [r0]
105 add r1, r1, r4
106 str r1, [r0]
So discard them to avoid touching the relocation entry in
arch/arm/lib/relocate.S.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Tom Warren <twarren@nvidia.com>
Cc: York Sun <yorksun@freescale.com>
Cc: Hans De Goede <hdegoede@redhat.com>
Cc: Ian Campbell <ijc@hellion.org.uk>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@konsulko.com>
Cc: Jan Kiszka <jan.kiszka@siemens.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2015-10-23 02:13:03 +00:00
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*/
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/DISCARD/ : { *(.rel._secure*) }
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ARM: Disable "DISCARD" for secure section if CONFIG_ARMV7_SECURE_BASE isn't defined
"DISCARD" will remove ._secure.text relocate, but PSCI framework
has already used some absolute address those need to relocate.
Use readelf -t -r u-boot show us:
.__secure_start addr: 601408e4
.__secure_end addr: 60141460
60141140 00000017 R_ARM_RELATIVE
46 _secure_monitor:
47 #ifdef CONFIG_ARMV7_PSCI
48 ldr r5, =_psci_vectors
60141194 00000017 R_ARM_RELATIVE
6014119c 00000017 R_ARM_RELATIVE
601411a4 00000017 R_ARM_RELATIVE
601411ac 00000017 R_ARM_RELATIVE
64 _psci_table:
66 .word psci_cpu_suspend
...
72 .word psci_migrate
60141344 00000017 R_ARM_RELATIVE
6014145c 00000017 R_ARM_RELATIVE
202 ldr r5, =psci_text_end
Solutions:
1. Change absolute address to RelAdr.
Based on LDR (immediate, ARM), we only have 4K offset to jump.
Now PSCI code size is close to 4K size that is LDR limit jump size,
so even if the LDR is based on the current instruction address,
there is also have a risk for RelAdr. If we use two jump steps I
think we can fix this issue, but looks too hack, so give up this way.
2. Enable "DISCARD" only for CONFIG_ARMV7_SECURE_BASE has defined.
If CONFIG_ARMV7_SECURE_BASE is defined in platform, all of secure
will in the BASE address that is absolute.
Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-18 03:02:40 +00:00
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#endif
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2012-02-23 03:28:41 +00:00
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. = 0x00000000;
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. = ALIGN(4);
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.text :
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{
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2013-06-11 12:17:33 +00:00
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*(.__image_copy_start)
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2014-04-15 14:13:51 +00:00
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*(.vectors)
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2012-10-22 06:19:32 +00:00
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CPUDIR/start.o (.text*)
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2018-06-12 05:48:37 +00:00
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}
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/* This needs to come before *(.text*) */
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.__efi_runtime_start : {
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*(.__efi_runtime_start)
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}
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.efi_runtime : {
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*(.text.efi_runtime*)
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*(.rodata.efi_runtime*)
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*(.data.efi_runtime*)
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}
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.__efi_runtime_stop : {
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*(.__efi_runtime_stop)
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}
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.text_rest :
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{
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2012-10-22 06:19:32 +00:00
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*(.text*)
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2012-02-23 03:28:41 +00:00
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}
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2015-04-21 05:18:24 +00:00
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#ifdef CONFIG_ARMV7_NONSEC
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2014-07-12 13:24:02 +00:00
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2016-06-19 04:38:34 +00:00
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/* Align the secure section only if we're going to use it in situ */
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2018-09-06 03:56:28 +00:00
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.__secure_start
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2016-06-19 04:38:34 +00:00
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#ifndef CONFIG_ARMV7_SECURE_BASE
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ALIGN(CONSTANT(COMMONPAGESIZE))
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#endif
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2018-09-06 03:56:28 +00:00
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: {
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2016-06-19 04:38:34 +00:00
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KEEP(*(.__secure_start))
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}
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2014-07-12 13:24:02 +00:00
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#ifndef CONFIG_ARMV7_SECURE_BASE
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#define CONFIG_ARMV7_SECURE_BASE
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2016-06-07 02:54:27 +00:00
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#define __ARMV7_PSCI_STACK_IN_RAM
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2014-07-12 13:24:02 +00:00
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#endif
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.secure_text CONFIG_ARMV7_SECURE_BASE :
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AT(ADDR(.__secure_start) + SIZEOF(.__secure_start))
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{
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*(._secure.text)
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}
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2016-07-05 13:45:06 +00:00
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.secure_data : AT(LOADADDR(.secure_text) + SIZEOF(.secure_text))
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{
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*(._secure.data)
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}
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2016-09-26 05:21:30 +00:00
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#ifdef CONFIG_ARMV7_PSCI
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2016-07-05 13:45:06 +00:00
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.secure_stack ALIGN(ADDR(.secure_data) + SIZEOF(.secure_data),
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2016-06-19 04:38:36 +00:00
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CONSTANT(COMMONPAGESIZE)) (NOLOAD) :
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2016-06-07 02:54:27 +00:00
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#ifdef __ARMV7_PSCI_STACK_IN_RAM
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2016-06-19 04:38:36 +00:00
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AT(ADDR(.secure_stack))
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#else
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2016-07-05 13:45:06 +00:00
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AT(LOADADDR(.secure_data) + SIZEOF(.secure_data))
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2016-06-19 04:38:36 +00:00
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#endif
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{
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KEEP(*(.__secure_stack_start))
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2016-09-26 05:21:30 +00:00
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2016-06-19 04:38:36 +00:00
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/* Skip addreses for stack */
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. = . + CONFIG_ARMV7_PSCI_NR_CPUS * ARM_PSCI_STACK_SIZE;
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2016-09-26 05:21:30 +00:00
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2016-06-19 04:38:36 +00:00
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/* Align end of stack section to page boundary */
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. = ALIGN(CONSTANT(COMMONPAGESIZE));
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KEEP(*(.__secure_stack_end))
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2016-06-19 04:38:39 +00:00
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#ifdef CONFIG_ARMV7_SECURE_MAX_SIZE
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/*
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* We are not checking (__secure_end - __secure_start) here,
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* as these are the load addresses, and do not include the
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* stack section. Instead, use the end of the stack section
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* and the start of the text section.
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*/
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ASSERT((. - ADDR(.secure_text)) <= CONFIG_ARMV7_SECURE_MAX_SIZE,
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"Error: secure section exceeds secure memory size");
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#endif
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2016-06-19 04:38:36 +00:00
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}
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#ifndef __ARMV7_PSCI_STACK_IN_RAM
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/* Reset VMA but don't allocate space if we have secure SRAM */
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. = LOADADDR(.secure_stack);
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2016-09-26 05:21:30 +00:00
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#endif
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2016-06-07 02:54:27 +00:00
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#endif
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2016-06-19 04:38:36 +00:00
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.__secure_end : AT(ADDR(.__secure_end)) {
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2014-07-12 13:24:02 +00:00
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*(.__secure_end)
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LONG(0x1d1071c); /* Must output something to reset LMA */
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}
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#endif
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2012-02-23 03:28:41 +00:00
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. = ALIGN(4);
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.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
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. = ALIGN(4);
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.data : {
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2012-10-22 06:19:32 +00:00
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*(.data*)
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2012-02-23 03:28:41 +00:00
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}
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. = ALIGN(4);
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. = .;
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2012-10-12 10:27:03 +00:00
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. = ALIGN(4);
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2022-05-30 10:00:04 +00:00
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__u_boot_list : {
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KEEP(*(SORT(__u_boot_list*)));
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2012-10-12 10:27:03 +00:00
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}
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2012-02-23 03:28:41 +00:00
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. = ALIGN(4);
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2016-03-04 00:10:01 +00:00
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.efi_runtime_rel_start :
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{
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*(.__efi_runtime_rel_start)
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}
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.efi_runtime_rel : {
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2018-06-12 05:48:37 +00:00
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*(.rel*.efi_runtime)
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*(.rel*.efi_runtime.*)
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2016-03-04 00:10:01 +00:00
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}
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.efi_runtime_rel_stop :
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{
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*(.__efi_runtime_rel_stop)
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}
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2017-06-14 13:13:21 +00:00
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. = ALIGN(4);
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2016-03-04 00:10:01 +00:00
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2013-06-11 12:17:33 +00:00
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.image_copy_end :
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{
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*(.__image_copy_end)
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}
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2012-02-23 03:28:41 +00:00
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|
|
2013-06-11 12:17:34 +00:00
|
|
|
.rel_dyn_start :
|
|
|
|
{
|
|
|
|
*(.__rel_dyn_start)
|
|
|
|
}
|
|
|
|
|
2012-02-23 03:28:41 +00:00
|
|
|
.rel.dyn : {
|
|
|
|
*(.rel*)
|
2013-06-11 12:17:34 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
.rel_dyn_end :
|
|
|
|
{
|
|
|
|
*(.__rel_dyn_end)
|
2012-02-23 03:28:41 +00:00
|
|
|
}
|
|
|
|
|
2014-02-22 16:53:42 +00:00
|
|
|
.end :
|
|
|
|
{
|
|
|
|
*(.__end)
|
|
|
|
}
|
|
|
|
|
|
|
|
_image_binary_end = .;
|
2012-02-23 03:28:41 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Deprecated: this MMU section is used by pxa at present but
|
|
|
|
* should not be used by new boards/CPUs.
|
|
|
|
*/
|
|
|
|
. = ALIGN(4096);
|
|
|
|
.mmutable : {
|
|
|
|
*(.mmutable)
|
|
|
|
}
|
|
|
|
|
2013-04-11 05:43:21 +00:00
|
|
|
/*
|
|
|
|
* Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
|
|
|
|
* __bss_base and __bss_limit are for linker only (overlay ordering)
|
|
|
|
*/
|
|
|
|
|
2013-02-25 00:58:59 +00:00
|
|
|
.bss_start __rel_dyn_start (OVERLAY) : {
|
|
|
|
KEEP(*(.__bss_start));
|
2013-04-11 05:43:21 +00:00
|
|
|
__bss_base = .;
|
2013-02-25 00:58:59 +00:00
|
|
|
}
|
|
|
|
|
2013-04-11 05:43:21 +00:00
|
|
|
.bss __bss_base (OVERLAY) : {
|
2012-10-22 06:19:32 +00:00
|
|
|
*(.bss*)
|
2012-02-23 03:28:41 +00:00
|
|
|
. = ALIGN(4);
|
2013-04-11 05:43:21 +00:00
|
|
|
__bss_limit = .;
|
2013-02-25 00:58:59 +00:00
|
|
|
}
|
2013-03-18 16:31:00 +00:00
|
|
|
|
2013-04-11 05:43:21 +00:00
|
|
|
.bss_end __bss_limit (OVERLAY) : {
|
|
|
|
KEEP(*(.__bss_end));
|
2012-02-23 03:28:41 +00:00
|
|
|
}
|
|
|
|
|
2014-02-22 16:53:42 +00:00
|
|
|
.dynsym _image_binary_end : { *(.dynsym) }
|
2013-11-07 13:21:46 +00:00
|
|
|
.dynbss : { *(.dynbss) }
|
|
|
|
.dynstr : { *(.dynstr*) }
|
|
|
|
.dynamic : { *(.dynamic*) }
|
|
|
|
.plt : { *(.plt*) }
|
|
|
|
.interp : { *(.interp*) }
|
2014-01-27 04:48:11 +00:00
|
|
|
.gnu.hash : { *(.gnu.hash) }
|
2013-11-07 13:21:46 +00:00
|
|
|
.gnu : { *(.gnu*) }
|
|
|
|
.ARM.exidx : { *(.ARM.exidx*) }
|
2014-01-13 13:57:05 +00:00
|
|
|
.gnu.linkonce.armexidx : { *(.gnu.linkonce.armexidx.*) }
|
2012-02-23 03:28:41 +00:00
|
|
|
}
|