2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2015-10-26 11:47:52 +00:00
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/*
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* Copyright 2015 Freescale Semiconductor
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*/
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#ifndef __CPLD_H__
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#define __CPLD_H__
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/*
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* CPLD register set of LS1043ARDB board-specific.
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*/
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struct cpld_data {
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u8 cpld_ver; /* 0x0 - CPLD Major Revision Register */
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u8 cpld_ver_sub; /* 0x1 - CPLD Minor Revision Register */
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u8 pcba_ver; /* 0x2 - PCBA Revision Register */
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u8 system_rst; /* 0x3 - system reset register */
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u8 soft_mux_on; /* 0x4 - Switch Control Enable Register */
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u8 cfg_rcw_src1; /* 0x5 - Reset config word 1 */
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u8 cfg_rcw_src2; /* 0x6 - Reset config word 1 */
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u8 vbank; /* 0x7 - Flash bank selection Control */
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u8 sysclk_sel; /* 0x8 - */
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u8 uart_sel; /* 0x9 - */
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u8 sd1refclk_sel; /* 0xA - */
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u8 tdmclk_mux_sel; /* 0xB - */
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u8 sdhc_spics_sel; /* 0xC - */
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u8 status_led; /* 0xD - */
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u8 global_rst; /* 0xE - */
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};
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u8 cpld_read(unsigned int reg);
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void cpld_write(unsigned int reg, u8 value);
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void cpld_rev_bit(unsigned char *value);
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#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
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#define CPLD_WRITE(reg, value) \
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cpld_write(offsetof(struct cpld_data, reg), value)
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/* CPLD on IFC */
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#define CPLD_SW_MUX_BANK_SEL 0x40
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#define CPLD_BANK_SEL_MASK 0x07
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#define CPLD_BANK_SEL_ALTBANK 0x04
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2016-04-25 08:38:35 +00:00
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#define CPLD_CFG_RCW_SRC_NOR 0x025
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2015-10-26 11:47:53 +00:00
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#define CPLD_CFG_RCW_SRC_NAND 0x106
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2022-09-26 08:18:49 +00:00
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#define CPLD_CFG_RCW_SRC_NAND_4K 0x118
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2015-10-26 11:47:56 +00:00
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#define CPLD_CFG_RCW_SRC_SD 0x040
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2015-10-26 11:47:52 +00:00
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#endif
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