2008-06-10 07:13:16 +00:00
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/*
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* Copyright (C) Matrix Vision GmbH 2008
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*
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* Matrix Vision mvBlueLYNX-M7 configuration file
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* based on Freescale's MPC8349ITX.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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2008-07-02 16:54:08 +00:00
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#include <version.h>
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2008-06-10 07:13:16 +00:00
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_E300 1
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2009-05-22 22:23:24 +00:00
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#define CONFIG_MPC83xx 1
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2009-05-22 22:23:25 +00:00
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#define CONFIG_MPC834x 1
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2008-06-10 07:13:16 +00:00
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#define CONFIG_MPC8343 1
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2010-10-06 07:05:45 +00:00
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#define CONFIG_SYS_TEXT_BASE 0xFFF00000
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_IMMR 0xE0000000
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2008-06-10 07:13:16 +00:00
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#define CONFIG_PCI
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#define CONFIG_PCI_SKIP_HOST_BRIDGE
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#define CONFIG_HARD_I2C
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#define CONFIG_TSEC_ENET
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#define CONFIG_MPC8XXX_SPI
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#define CONFIG_HARD_SPI
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#define MVBLM7_MMC_CS 0x04000000
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2009-08-27 12:48:35 +00:00
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#define CONFIG_MISC_INIT_R
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2008-06-10 07:13:16 +00:00
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/* I2C */
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#define CONFIG_FSL_I2C
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#define CONFIG_I2C_MULTI_BUS
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_I2C_OFFSET 0x3000
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#define CONFIG_SYS_I2C2_OFFSET 0x3100
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2008-06-10 07:13:16 +00:00
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_I2C_SPEED 100000
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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2008-06-10 07:13:16 +00:00
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/*
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* DDR Setup
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*/
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2009-08-27 12:48:35 +00:00
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#undef CONFIG_SPD_EEPROM
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_DDR_BASE 0x00000000
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
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#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
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#define CONFIG_SYS_83XX_DDR_USES_CS0 1
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#define CONFIG_SYS_MEMTEST_START (60<<20)
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#define CONFIG_SYS_MEMTEST_END (70<<20)
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2009-08-27 12:48:35 +00:00
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#define CONFIG_VERY_BIG_RAM
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2008-10-16 13:01:15 +00:00
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2009-08-27 12:48:35 +00:00
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#define CONFIG_SYS_DDRCDR 0x22000001
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#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
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2008-06-10 07:13:16 +00:00
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2009-08-27 12:48:35 +00:00
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#define CONFIG_SYS_DDR_SIZE 512
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2008-06-10 07:13:16 +00:00
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2009-08-27 12:48:35 +00:00
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#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
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2008-06-10 07:13:16 +00:00
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2009-08-27 12:48:35 +00:00
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#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
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2008-06-10 07:13:16 +00:00
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2009-08-27 12:48:35 +00:00
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#define CONFIG_SYS_DDR_TIMING_0 0x00260802
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#define CONFIG_SYS_DDR_TIMING_1 0x3837c322
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#define CONFIG_SYS_DDR_TIMING_2 0x0f9848c6
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#define CONFIG_SYS_DDR_TIMING_3 0x00000000
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2008-06-10 07:13:16 +00:00
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2009-08-27 12:48:35 +00:00
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#define CONFIG_SYS_DDR_SDRAM_CFG 0x43080008
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
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2009-08-27 12:48:35 +00:00
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#define CONFIG_SYS_DDR_INTERVAL 0x02000100
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2008-06-10 07:13:16 +00:00
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2009-08-27 12:48:35 +00:00
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#define CONFIG_SYS_DDR_MODE 0x04040242
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#define CONFIG_SYS_DDR_MODE2 0x00800000
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2008-06-10 07:13:16 +00:00
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/* Flash */
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_FLASH_CFI
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2008-08-12 23:40:42 +00:00
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#define CONFIG_FLASH_CFI_DRIVER
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
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#define CONFIG_SYS_FLASH_BASE 0xFF800000
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#define CONFIG_SYS_FLASH_SIZE 8
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#define CONFIG_SYS_FLASH_SIZE_SHIFT 3
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 256
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#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V)
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#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
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2008-06-10 18:25:24 +00:00
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OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS|\
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2008-06-10 07:13:16 +00:00
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OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | \
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OR_GPCM_EAD)
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CONFIG_SYS_FLASH_SIZE_SHIFT))
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2008-06-10 07:13:16 +00:00
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/*
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* U-Boot memory configuration
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*/
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2010-10-07 19:51:12 +00:00
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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2008-10-16 13:01:15 +00:00
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#undef CONFIG_SYS_RAMBOOT
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2008-06-10 07:13:16 +00:00
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_INIT_RAM_LOCK
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#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
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2010-10-26 11:32:32 +00:00
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
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2008-06-10 07:13:16 +00:00
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2010-10-26 12:34:52 +00:00
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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2008-06-10 07:13:16 +00:00
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2008-10-16 13:01:15 +00:00
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/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
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#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
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2008-06-10 07:13:16 +00:00
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/*
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* Local Bus LCRR and LBCR regs
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* LCRR: DLL bypass, Clock divider is 4
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* External Local Bus rate is
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* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
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*/
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2009-09-25 23:19:44 +00:00
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#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
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#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_LBC_LBCR 0x00000000
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2008-06-10 07:13:16 +00:00
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/* LB sdram refresh timer, about 6us */
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_LBC_LSRT 0x32000000
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2008-06-10 07:13:16 +00:00
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/* LB refresh timer prescal, 266MHz/32*/
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_LBC_MRTPR 0x20000000
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2008-06-10 07:13:16 +00:00
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/*
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* Serial Port
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*/
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#define CONFIG_CONS_INDEX 1
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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2008-06-10 07:13:16 +00:00
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_BAUDRATE_TABLE \
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2008-06-10 07:13:16 +00:00
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
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#define CONFIG_CONSOLE ttyS0
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#define CONFIG_BAUDRATE 115200
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
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2008-06-10 07:13:16 +00:00
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/* pass open firmware flat tree */
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_OF_BOARD_SETUP 1
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#define CONFIG_OF_STDOUT_VIA_ALIAS 1
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#define MV_DTB_NAME "mvblm7.dtb"
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/*
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* PCI
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*/
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
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#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
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#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
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#define CONFIG_SYS_PCI1_MMIO_BASE (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
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#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
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#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000
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#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
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#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
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#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000
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2008-06-10 07:13:16 +00:00
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#define CONFIG_NET_RETRY_COUNT 3
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2010-10-06 07:05:45 +00:00
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#define CONFIG_PCI_66M
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2008-06-10 07:13:16 +00:00
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#define CONFIG_83XX_CLKIN 66666667
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#define CONFIG_PCI_PNP
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#define CONFIG_PCI_SCAN_SHOW
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/* TSEC */
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#define CONFIG_GMII
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_VSC8601_SKEWFIX
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#define CONFIG_SYS_VSC8601_SKEW_TX 3
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#define CONFIG_SYS_VSC8601_SKEW_RX 3
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2008-06-10 07:13:16 +00:00
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#define CONFIG_TSEC1
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#define CONFIG_TSEC2
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#define CONFIG_HAS_ETH0
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#define CONFIG_TSEC1_NAME "TSEC0"
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#define CONFIG_FEC1_PHY_NORXERR
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_TSEC1_OFFSET 0x24000
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#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
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2008-06-10 07:13:16 +00:00
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#define TSEC1_PHY_ADDR 0x10
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#define TSEC1_PHYIDX 0
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#define TSEC1_FLAGS (TSEC_GIGABIT|TSEC_REDUCED)
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#define CONFIG_HAS_ETH1
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#define CONFIG_TSEC2_NAME "TSEC1"
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#define CONFIG_FEC2_PHY_NORXERR
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_TSEC2_OFFSET 0x25000
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#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
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2008-06-10 07:13:16 +00:00
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#define TSEC2_PHY_ADDR 0x11
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#define TSEC2_PHYIDX 0
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#define TSEC2_FLAGS (TSEC_GIGABIT|TSEC_REDUCED)
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#define CONFIG_ETHPRIME "TSEC0"
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#define CONFIG_BOOTP_VENDOREX
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#define CONFIG_BOOTP_SUBNETMASK
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_DNS
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#define CONFIG_BOOTP_DNS2
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#define CONFIG_BOOTP_HOSTNAME
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_NTPSERVER
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#define CONFIG_BOOTP_RANDOM_DELAY
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#define CONFIG_BOOTP_SEND_HOSTNAME
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/* USB */
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2010-05-03 11:22:31 +00:00
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#define CONFIG_SYS_USB_HOST
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#define CONFIG_USB_EHCI
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#define CONFIG_USB_EHCI_FSL
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2008-06-10 07:13:16 +00:00
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#define CONFIG_HAS_FSL_DR_USB
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2010-05-03 11:22:31 +00:00
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#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
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2008-06-10 07:13:16 +00:00
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/*
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* Environment
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*/
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2008-10-16 13:01:15 +00:00
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#undef CONFIG_SYS_FLASH_PROTECTION
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2008-06-10 07:13:16 +00:00
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#define CONFIG_ENV_OVERWRITE
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2008-09-10 20:48:04 +00:00
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#define CONFIG_ENV_IS_IN_FLASH 1
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2008-09-10 20:48:06 +00:00
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#define CONFIG_ENV_ADDR 0xFF800000
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_SECT_SIZE 0x2000
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
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#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
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2008-06-10 07:13:16 +00:00
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2008-06-28 21:34:37 +00:00
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#define CONFIG_LOADS_ECHO
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_LOADS_BAUD_CHANGE
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2008-06-10 07:13:16 +00:00
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_SDRAM
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_FPGA
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2010-05-03 11:22:31 +00:00
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#define CONFIG_CMD_USB
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#define CONFIG_DOS_PARTITION
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2008-06-10 07:13:16 +00:00
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#undef CONFIG_WATCHDOG
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/*
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* Miscellaneous configurable options
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*/
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_LONGHELP
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2008-06-10 07:13:16 +00:00
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#define CONFIG_CMDLINE_EDITING
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2010-04-15 22:36:05 +00:00
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#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
|
2008-10-16 13:01:15 +00:00
|
|
|
#define CONFIG_SYS_HUSH_PARSER
|
|
|
|
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
2008-06-10 07:13:16 +00:00
|
|
|
|
|
|
|
/* default load address */
|
2008-10-16 13:01:15 +00:00
|
|
|
#define CONFIG_SYS_LOAD_ADDR 0x2000000
|
2008-06-10 07:13:16 +00:00
|
|
|
/* default location for tftp and bootm */
|
|
|
|
#define CONFIG_LOADADDR 0x200000
|
|
|
|
|
2008-10-16 13:01:15 +00:00
|
|
|
#define CONFIG_SYS_PROMPT "mvBL-M7> "
|
|
|
|
#define CONFIG_SYS_CBSIZE 256
|
2008-06-10 07:13:16 +00:00
|
|
|
|
2008-10-16 13:01:15 +00:00
|
|
|
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
|
|
|
|
#define CONFIG_SYS_MAXARGS 16
|
|
|
|
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
|
|
|
#define CONFIG_SYS_HZ 1000
|
2008-06-10 07:13:16 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* For booting Linux, the board info and command line data
|
2010-09-10 22:42:32 +00:00
|
|
|
* have to be in the first 256 MB of memory, since this is
|
2008-06-10 07:13:16 +00:00
|
|
|
* the maximum mapped by the Linux kernel during initialization.
|
|
|
|
*/
|
2010-09-10 22:42:32 +00:00
|
|
|
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/
|
2008-06-10 07:13:16 +00:00
|
|
|
|
2008-10-16 13:01:15 +00:00
|
|
|
#define CONFIG_SYS_HRCW_LOW 0x0
|
|
|
|
#define CONFIG_SYS_HRCW_HIGH 0x0
|
2008-06-10 07:13:16 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* System performance
|
|
|
|
*/
|
2008-10-16 13:01:15 +00:00
|
|
|
#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
|
|
|
|
#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
|
|
|
|
#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
|
|
|
|
#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
|
2008-06-10 07:13:16 +00:00
|
|
|
|
|
|
|
/* clocking */
|
2008-10-16 13:01:15 +00:00
|
|
|
#define CONFIG_SYS_SCCR_ENCCM 0
|
|
|
|
#define CONFIG_SYS_SCCR_USBMPHCM 0
|
|
|
|
#define CONFIG_SYS_SCCR_USBDRCM 2
|
|
|
|
#define CONFIG_SYS_SCCR_TSEC1CM 1
|
|
|
|
#define CONFIG_SYS_SCCR_TSEC2CM 1
|
2008-06-10 07:13:16 +00:00
|
|
|
|
2010-10-22 09:21:46 +00:00
|
|
|
#define CONFIG_SYS_SICRH 0x1fef0003
|
2008-10-16 13:01:15 +00:00
|
|
|
#define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1 | SICRL_USB0)
|
2008-06-10 07:13:16 +00:00
|
|
|
|
2008-10-16 13:01:15 +00:00
|
|
|
#define CONFIG_SYS_HID0_INIT 0x000000000
|
mpc83xx: turn on icache in core initialization to improve u-boot boot time
before, MPC8349ITX boots u-boot in 4.3sec:
column1 is elapsed time since first message
column2 is elapsed time since previous message
column3 is the message
0.000 0.000: U-Boot 2010.03-00126-gfd4e49c (Apr 11 2010 - 17:25:29) MPC83XX
0.000 0.000:
0.000 0.000: Reset Status:
0.000 0.000:
0.032 0.032: CPU: e300c1, MPC8349E, Rev: 1.1 at 533.333 MHz, CSB: 266.667 MHz
0.032 0.000: Board: Freescale MPC8349E-mITX
0.032 0.000: UPMA: Configured for compact flash
0.032 0.000: I2C: ready
0.061 0.028: DRAM: 256 MB (DDR1, 64-bit, ECC off, 266.667 MHz)
1.516 1.456: FLASH: 16 MB
2.641 1.125: PCI: Bus Dev VenId DevId Class Int
2.652 0.011: 00 10 1095 3114 0180 00
2.652 0.000: PCI: Bus Dev VenId DevId Class Int
2.652 0.000: In: serial
2.652 0.000: Out: serial
2.652 0.000: Err: serial
2.682 0.030: Board revision: 1.0 (PCF8475A)
3.080 0.398: Net: TSEC1: No support for PHY id ffffffff; assuming generic
3.080 0.000: TSEC0, TSEC1
4.300 1.219: IDE: Bus 0: .** Timeout **
after, MPC8349ITX boots u-boot in 3.0sec:
0.010 0.010: U-Boot 2010.03-00127-g4b468cc-dirty (Apr 11 2010 - 17:47:29) MPC83XX
0.010 0.000:
0.010 0.000: Reset Status:
0.010 0.000:
0.017 0.007: CPU: e300c1, MPC8349E, Rev: 1.1 at 533.333 MHz, CSB: 266.667 MHz
0.017 0.000: Board: Freescale MPC8349E-mITX
0.038 0.020: UPMA: Configured for compact flash
0.038 0.000: I2C: ready
0.038 0.000: DRAM: 256 MB (DDR1, 64-bit, ECC off, 266.667 MHz)
0.260 0.222: FLASH: 16 MB
1.390 1.130: PCI: Bus Dev VenId DevId Class Int
1.390 0.000: 00 10 1095 3114 0180 00
1.390 0.000: PCI: Bus Dev VenId DevId Class Int
1.400 0.010: In: serial
1.400 0.000: Out: serial
1.400 0.000: Err: serial
1.400 0.000: Board revision: 1.0 (PCF8475A)
1.832 0.432: Net: TSEC1: No support for PHY id ffffffff; assuming generic
1.832 0.000: TSEC0, TSEC1
3.038 1.205: IDE: Bus 0: .** Timeout **
also tested on these boards (albeit with a less accurate
boottime measurement method):
seconds: before after
8349MDS ~2.6 ~2.2
8360MDS ~2.8 ~2.6
8313RDB ~2.5 ~2.3 #nand boot
837xRDB ~3.1 ~2.3
also tested on an 8323ERDB.
v2: also remove the delayed icache enablement assumption in arch ppc's
board.c, and add a CONFIG_MPC83xx define in the ITX config file for
consistency (even though it was already being defined in 83xx'
config.mk).
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-04-21 00:37:54 +00:00
|
|
|
#define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \
|
|
|
|
HID0_ENABLE_INSTRUCTION_CACHE)
|
2008-06-10 07:13:16 +00:00
|
|
|
|
2008-10-16 13:01:15 +00:00
|
|
|
#define CONFIG_SYS_HID2 HID2_HBE
|
2008-07-02 16:54:08 +00:00
|
|
|
#define CONFIG_HIGH_BATS 1
|
2008-06-10 07:13:16 +00:00
|
|
|
|
|
|
|
/* DDR */
|
2008-10-16 13:01:15 +00:00
|
|
|
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
|
|
|
|
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
|
2008-06-10 07:13:16 +00:00
|
|
|
|
|
|
|
/* PCI */
|
2008-10-16 13:01:15 +00:00
|
|
|
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
|
|
|
|
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
|
|
|
|
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT |\
|
2008-06-10 07:13:16 +00:00
|
|
|
BATL_GUARDEDSTORAGE)
|
2008-10-16 13:01:15 +00:00
|
|
|
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
|
2008-06-10 07:13:16 +00:00
|
|
|
|
|
|
|
/* no PCI2 */
|
2008-10-16 13:01:15 +00:00
|
|
|
#define CONFIG_SYS_IBAT3L 0
|
|
|
|
#define CONFIG_SYS_IBAT3U 0
|
|
|
|
#define CONFIG_SYS_IBAT4L 0
|
|
|
|
#define CONFIG_SYS_IBAT4U 0
|
2008-06-10 07:13:16 +00:00
|
|
|
|
|
|
|
/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
|
2008-10-16 13:01:15 +00:00
|
|
|
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | \
|
2008-06-10 07:13:16 +00:00
|
|
|
BATL_GUARDEDSTORAGE)
|
2008-10-16 13:01:15 +00:00
|
|
|
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
|
2008-06-10 07:13:16 +00:00
|
|
|
|
|
|
|
/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFF800000 */
|
2009-03-31 22:49:36 +00:00
|
|
|
#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \
|
|
|
|
BATL_GUARDEDSTORAGE)
|
2008-10-16 13:01:15 +00:00
|
|
|
#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
|
|
|
|
#define CONFIG_SYS_IBAT7L 0
|
|
|
|
#define CONFIG_SYS_IBAT7U 0
|
|
|
|
|
|
|
|
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
|
|
|
|
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
|
|
|
|
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
|
|
|
|
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
|
|
|
|
#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
|
|
|
|
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
|
|
|
|
#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
|
|
|
|
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
|
|
|
|
#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
|
|
|
|
#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
|
|
|
|
#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
|
|
|
|
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
|
|
|
|
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
|
|
|
|
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
|
|
|
|
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
|
|
|
|
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
|
2008-06-10 07:13:16 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Environment Configuration
|
|
|
|
*/
|
|
|
|
#define CONFIG_ENV_OVERWRITE
|
|
|
|
|
|
|
|
#define CONFIG_NETDEV eth0
|
|
|
|
|
|
|
|
/* Default path and filenames */
|
|
|
|
#define CONFIG_BOOTDELAY 5
|
|
|
|
#define CONFIG_AUTOBOOT_KEYED
|
|
|
|
#define CONFIG_AUTOBOOT_STOP_STR "s"
|
|
|
|
#define CONFIG_ZERO_BOOTDELAY_CHECK
|
|
|
|
#define CONFIG_RESET_TO_RETRY 1000
|
|
|
|
|
2008-08-20 09:11:52 +00:00
|
|
|
#define MV_CI mvBL-M7
|
|
|
|
#define MV_VCI mvBL-M7
|
2009-08-27 12:48:35 +00:00
|
|
|
#define MV_FPGA_DATA 0xfff40000
|
|
|
|
#define MV_FPGA_SIZE 0
|
2008-08-20 09:11:52 +00:00
|
|
|
#define MV_KERNEL_ADDR 0xff810000
|
|
|
|
#define MV_INITRD_ADDR 0xffb00000
|
2009-09-17 02:38:10 +00:00
|
|
|
#define MV_SCRIPT_ADDR 0xff804000
|
|
|
|
#define MV_SCRIPT_ADDR2 0xff806000
|
2008-08-20 09:11:52 +00:00
|
|
|
#define MV_DTB_ADDR 0xff808000
|
|
|
|
#define MV_INITRD_LENGTH 0x00400000
|
2008-06-10 07:13:16 +00:00
|
|
|
|
|
|
|
#define CONFIG_SHOW_BOOT_PROGRESS 1
|
|
|
|
|
2008-08-20 09:11:52 +00:00
|
|
|
#define MV_KERNEL_ADDR_RAM 0x00100000
|
|
|
|
#define MV_DTB_ADDR_RAM 0x00600000
|
|
|
|
#define MV_INITRD_ADDR_RAM 0x01000000
|
2008-06-10 07:13:16 +00:00
|
|
|
|
2009-09-17 02:38:10 +00:00
|
|
|
#define CONFIG_BOOTCOMMAND "if imi ${script_addr}; \
|
|
|
|
then source ${script_addr}; \
|
|
|
|
else source ${script_addr2}; \
|
2008-06-10 07:13:16 +00:00
|
|
|
fi;"
|
|
|
|
#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs"
|
|
|
|
|
|
|
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
|
|
"console_nr=0\0" \
|
2008-08-20 09:11:52 +00:00
|
|
|
"baudrate=" MK_STR(CONFIG_BAUDRATE) "\0" \
|
2008-06-10 07:13:16 +00:00
|
|
|
"stdin=serial\0" \
|
|
|
|
"stdout=serial\0" \
|
|
|
|
"stderr=serial\0" \
|
|
|
|
"fpga=0\0" \
|
2008-08-20 09:11:52 +00:00
|
|
|
"fpgadata=" MK_STR(MV_FPGA_DATA) "\0" \
|
|
|
|
"fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0" \
|
2009-09-17 02:38:10 +00:00
|
|
|
"script_addr=" MK_STR(MV_SCRIPT_ADDR) "\0" \
|
|
|
|
"script_addr2=" MK_STR(MV_SCRIPT_ADDR2) "\0" \
|
2008-08-20 09:11:52 +00:00
|
|
|
"mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0" \
|
|
|
|
"mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0" \
|
|
|
|
"mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0" \
|
|
|
|
"mv_initrd_addr_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0" \
|
|
|
|
"mv_initrd_length=" MK_STR(MV_INITRD_LENGTH) "\0" \
|
|
|
|
"mv_dtb_addr=" MK_STR(MV_DTB_ADDR) "\0" \
|
|
|
|
"mv_dtb_addr_ram=" MK_STR(MV_DTB_ADDR_RAM) "\0" \
|
|
|
|
"dtb_name=" MK_STR(MV_DTB_NAME) "\0" \
|
2008-07-02 16:54:08 +00:00
|
|
|
"mv_version=" U_BOOT_VERSION "\0" \
|
2008-08-20 09:11:52 +00:00
|
|
|
"dhcp_client_id=" MK_STR(MV_CI) "\0" \
|
|
|
|
"dhcp_vendor-class-identifier=" MK_STR(MV_VCI) "\0" \
|
2008-06-10 07:13:16 +00:00
|
|
|
"netretry=no\0" \
|
|
|
|
"use_static_ipaddr=no\0" \
|
|
|
|
"static_ipaddr=192.168.90.10\0" \
|
|
|
|
"static_netmask=255.255.255.0\0" \
|
|
|
|
"static_gateway=0.0.0.0\0" \
|
2009-08-27 12:48:35 +00:00
|
|
|
"initrd_name=uInitrd.mvBL-M7-rfs\0" \
|
2008-06-10 07:13:16 +00:00
|
|
|
"zcip=no\0" \
|
|
|
|
"netboot=yes\0" \
|
|
|
|
"mvtest=Ff\0" \
|
|
|
|
"tried_bootfromflash=no\0" \
|
|
|
|
"tried_bootfromnet=no\0" \
|
|
|
|
"bootfile=mvblm72625.boot\0" \
|
|
|
|
"use_dhcp=yes\0" \
|
|
|
|
"gev_start=yes\0" \
|
|
|
|
"mvbcdma_debug=0\0" \
|
|
|
|
"mvbcia_debug=0\0" \
|
|
|
|
"propdev_debug=0\0" \
|
|
|
|
"gevss_debug=0\0" \
|
|
|
|
"watchdog=0\0" \
|
|
|
|
"usb_dr_mode=host\0" \
|
2008-08-20 09:11:52 +00:00
|
|
|
"sensor_cnt=2\0" \
|
2008-06-10 07:13:16 +00:00
|
|
|
""
|
|
|
|
|
|
|
|
#define CONFIG_FPGA_COUNT 1
|
2008-10-16 13:01:15 +00:00
|
|
|
#define CONFIG_FPGA CONFIG_SYS_ALTERA_CYCLON2
|
2008-06-10 07:13:16 +00:00
|
|
|
#define CONFIG_FPGA_ALTERA
|
|
|
|
#define CONFIG_FPGA_CYCLON2
|
|
|
|
|
|
|
|
#endif
|