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39 lines
956 B
C
39 lines
956 B
C
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
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*/
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#ifndef _TILCDC_H
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#define _TILCDC_H
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/**
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* tilcdc_panel_info: Panel parameters
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*
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* @ac_bias: AC Bias Pin Frequency
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* @ac_bias_intrpt: AC Bias Pin Transitions per Interrupt
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* @dma_burst_sz: DMA burst size
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* @bpp: Bits per pixel
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* @fdd: FIFO DMA Request Delay
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* @tft_alt_mode: TFT Alternative Signal Mapping (Only for active)
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* @invert_pxl_clk: Invert pixel clock
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* @sync_edge: Horizontal and Vertical Sync Edge: 0=rising 1=falling
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* @sync_ctrl: Horizontal and Vertical Sync: Control: 0=ignore
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* @raster_order: Raster Data Order Select: 1=Most-to-least 0=Least-to-most
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* @fifo_th: DMA FIFO threshold
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*/
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struct tilcdc_panel_info {
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u32 ac_bias;
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u32 ac_bias_intrpt;
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u32 dma_burst_sz;
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u32 bpp;
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u32 fdd;
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bool tft_alt_mode;
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bool invert_pxl_clk;
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u32 sync_edge;
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u32 sync_ctrl;
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u32 raster_order;
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u32 fifo_th;
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};
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#endif /* _TILCDC_H */
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