2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2017-11-23 13:47:48 +00:00
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/*
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* Configuation settings for the WB50N CPU Module.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <asm/hardware.h>
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/* ARM asynchronous clock */
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#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
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#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
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#define CONFIG_ARCH_CPU_INIT
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#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#ifndef CONFIG_SPL_BUILD
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#endif
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/* general purpose I/O */
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#define CONFIG_AT91_GPIO
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/* serial console */
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#define CONFIG_ATMEL_USART
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#define CONFIG_USART_BASE ATMEL_BASE_DBGU
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#define CONFIG_USART_ID ATMEL_ID_DBGU
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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/* SDRAM */
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#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
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#define CONFIG_SYS_SDRAM_SIZE 0x04000000
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SYS_INIT_SP_ADDR 0x310000
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#else
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
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#endif
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#define CONFIG_SYS_MEMTEST_START 0x21000000
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#define CONFIG_SYS_MEMTEST_END 0x22000000
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/* NAND flash */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
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/* our ALE is AD21 */
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#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
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/* our CLE is AD22 */
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#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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/* Ethernet Hardware */
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#define CONFIG_MACB
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#define CONFIG_RMII
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#define CONFIG_NET_RETRY_COUNT 20
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#define CONFIG_MACB_SEARCH_PHY
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#define CONFIG_RGMII
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#define CONFIG_ETHADDR C0:EE:40:00:00:00
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#define CONFIG_ENV_OVERWRITE 1
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#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"autoload=no\0" \
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"autostart=no\0"
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/* bootstrap + u-boot + env in nandflash */
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#define CONFIG_ENV_OFFSET_REDUND 0xC0000
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#define CONFIG_BOOTCOMMAND \
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"nand read 0x22000000 0x000e0000 0x500000; " \
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"bootm"
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#define CONFIG_BOOTARGS \
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"rw rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs"
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_CBSIZE 1024
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_PBSIZE \
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(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
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/* SPL */
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#define CONFIG_SPL_MAX_SIZE 0x10000
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#define CONFIG_SPL_BSS_START_ADDR 0x20000000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
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#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
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#define CONFIG_SYS_MONITOR_LEN (512 << 10)
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#define CONFIG_SPL_NAND_DRIVERS
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#define CONFIG_SPL_NAND_BASE
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
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#define CONFIG_SYS_NAND_PAGE_COUNT 64
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
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#endif
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