u-boot/arch/nios2/include/asm/cache.h

/*
 * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
 * Scott McNutt <smcnutt@psyent.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __ASM_NIOS2_CACHE_H_
#define __ASM_NIOS2_CACHE_H_

/*
 * Valid L1 data cache line sizes for the NIOS2 architecture are 4,
 * 16, and 32 bytes. We default to the largest of these values for
 * alignment of DMA buffers.
 */
#define ARCH_DMA_MINALIGN	32

#endif /* __ASM_NIOS2_CACHE_H_ */
Patches by Scott McNutt, 24 Aug 2004: - Add support for Altera Nios-II processors. - Add support for Psyent PCI-5441 board. - Add support for Psyent PK1C20 board. 2004-10-10 21:27:30 +00:00			`/*`
			`* (C) Copyright 2004, Psyent Corporation <www.psyent.com>`
			`* Scott McNutt <smcnutt@psyent.com>`
			`*`
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> 2013-07-08 07:37:19 +00:00			`* SPDX-License-Identifier: GPL-2.0+`
Patches by Scott McNutt, 24 Aug 2004: - Add support for Altera Nios-II processors. - Add support for Psyent PCI-5441 board. - Add support for Psyent PK1C20 board. 2004-10-10 21:27:30 +00:00			`*/`

			`#ifndef __ASM_NIOS2_CACHE_H_`
			`#define __ASM_NIOS2_CACHE_H_`

nios2: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment Signed-off-by: Anton Staaf <robotboy@chromium.org> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Scott McNutt <smcnutt@psyent.com> 2011-10-17 23:46:05 +00:00			`/*`
nios2: convert cache flush to use dm cpu data Convert cache flush to use dm cpu data. The original cache flush functions are written in assembly and use CONFIG_SYS_{I,D}CACHE_SIZE... macros. It is difficult to convert to use cache configuration in dm cpu data which is extracted from device tree. The cacheflush.c of Linux nios2 arch uses cpuinfo structure, which is very close to our dm cpu data. So we copy and modify it to arch/nios2/lib/cache.c to replace the old cache.S. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> 2015-10-22 23:58:20 +00:00			`* Valid L1 data cache line sizes for the NIOS2 architecture are 4,`
			`* 16, and 32 bytes. We default to the largest of these values for`
			`* alignment of DMA buffers.`
nios2: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment Signed-off-by: Anton Staaf <robotboy@chromium.org> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Scott McNutt <smcnutt@psyent.com> 2011-10-17 23:46:05 +00:00			`*/`
			`#define ARCH_DMA_MINALIGN 32`

Patches by Scott McNutt, 24 Aug 2004: - Add support for Altera Nios-II processors. - Add support for Psyent PCI-5441 board. - Add support for Psyent PK1C20 board. 2004-10-10 21:27:30 +00:00			`#endif /* __ASM_NIOS2_CACHE_H_ */`