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u-boot/arch/x86/lib/fsp2/fsp_silicon_init.c

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x86: fsp: Add FSP2 base support Add support for some important configuration options and FSP memory init. The memory init uses swizzle tables from the device tree. Support for the FSP_S binary is also included. Bootstage timing is used for both FSP_M and FSP_S and memory-mapped SPI reads. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-07 04:42:18 +00:00
// SPDX-License-Identifier: Intel
/*
* Copyright (C) 2015-2016 Intel Corp.
* (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
*
* Mostly taken from coreboot fsp2_0/silicon_init.c
*/
#define LOG_CATEGORY UCLASS_NORTHBRIDGE
#include <common.h>
#include <binman.h>
common: Drop bootstage.h from common header Move this fairly uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-10 17:40:00 +00:00
#include <bootstage.h>
x86: fsp: Add FSP2 base support Add support for some important configuration options and FSP memory init. The memory init uses swizzle tables from the device tree. Support for the FSP_S binary is also included. Bootstage timing is used for both FSP_M and FSP_S and memory-mapped SPI reads. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-07 04:42:18 +00:00
#include <dm.h>
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-10 17:40:05 +00:00
#include <log.h>
x86: fsp: Add FSP2 base support Add support for some important configuration options and FSP memory init. The memory init uses swizzle tables from the device tree. Support for the FSP_S binary is also included. Bootstage timing is used for both FSP_M and FSP_S and memory-mapped SPI reads. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-07 04:42:18 +00:00
#include <asm/arch/fsp/fsp_configs.h>
#include <asm/arch/fsp/fsp_s_upd.h>
#include <asm/fsp/fsp_infoheader.h>
#include <asm/fsp2/fsp_internal.h>
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2020-10-31 03:38:53 +00:00
#include <asm/global_data.h>
x86: fsp: Add FSP2 base support Add support for some important configuration options and FSP memory init. The memory init uses swizzle tables from the device tree. Support for the FSP_S binary is also included. Bootstage timing is used for both FSP_M and FSP_S and memory-mapped SPI reads. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-07 04:42:18 +00:00
int fsp_silicon_init(bool s3wake, bool use_spi_flash)
{
struct fsps_upd upd, *fsp_upd;
fsp_silicon_init_func func;
struct fsp_header *hdr;
struct binman_entry entry;
struct udevice *dev;
ulong rom_offset = 0;
x86: fsp: Add more debugging for silicon init If locating the FSP header hangs for whatever reason it is useful to see where it got stuck. Add a debug print. Also show the address of the FSP-S entry point as a sanity check. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-22 18:45:37 +00:00
u32 init_addr;
x86: fsp: Add FSP2 base support Add support for some important configuration options and FSP memory init. The memory init uses swizzle tables from the device tree. Support for the FSP_S binary is also included. Bootstage timing is used for both FSP_M and FSP_S and memory-mapped SPI reads. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-07 04:42:18 +00:00
int ret;
x86: fsp: Add more debugging for silicon init If locating the FSP header hangs for whatever reason it is useful to see where it got stuck. Add a debug print. Also show the address of the FSP-S entry point as a sanity check. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-22 18:45:37 +00:00
log_debug("Locating FSP\n");
x86: fsp: Add FSP2 base support Add support for some important configuration options and FSP memory init. The memory init uses swizzle tables from the device tree. Support for the FSP_S binary is also included. Bootstage timing is used for both FSP_M and FSP_S and memory-mapped SPI reads. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-07 04:42:18 +00:00
ret = fsp_locate_fsp(FSP_S, &entry, use_spi_flash, &dev, &hdr,
&rom_offset);
if (ret)
return log_msg_ret("locate FSP", ret);
x86: apl: Use memory-mapped access for VBT Use the new binman memory-mapping function to access the VBT, to simplify the code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-08 03:32:25 +00:00
binman_set_rom_offset(rom_offset);
x86: fsp: Add FSP2 base support Add support for some important configuration options and FSP memory init. The memory init uses swizzle tables from the device tree. Support for the FSP_S binary is also included. Bootstage timing is used for both FSP_M and FSP_S and memory-mapped SPI reads. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-07 04:42:18 +00:00
gd->arch.fsp_s_hdr = hdr;
/* Copy over the default config */
fsp_upd = (struct fsps_upd *)(hdr->img_base + hdr->cfg_region_off);
if (fsp_upd->header.signature != FSPS_UPD_SIGNATURE)
return log_msg_ret("Bad UPD signature", -EPERM);
memcpy(&upd, fsp_upd, sizeof(upd));
ret = fsps_update_config(dev, rom_offset, &upd);
if (ret)
return log_msg_ret("Could not setup config", ret);
x86: fsp: Add more debugging for silicon init If locating the FSP header hangs for whatever reason it is useful to see where it got stuck. Add a debug print. Also show the address of the FSP-S entry point as a sanity check. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-22 18:45:37 +00:00
log_debug("Silicon init @ %x...", init_addr);
bootstage: Use BOOTSTAGE instead of BOOTSTATE Some of the enum members are wrong. Fix them. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-10 17:39:59 +00:00
bootstage_start(BOOTSTAGE_ID_ACCUM_FSP_S, "fsp-s");
x86: fsp: Add FSP2 base support Add support for some important configuration options and FSP memory init. The memory init uses swizzle tables from the device tree. Support for the FSP_S binary is also included. Bootstage timing is used for both FSP_M and FSP_S and memory-mapped SPI reads. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-07 04:42:18 +00:00
func = (fsp_silicon_init_func)(hdr->img_base + hdr->fsp_silicon_init);
ret = func(&upd);
bootstage: Use BOOTSTAGE instead of BOOTSTATE Some of the enum members are wrong. Fix them. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-10 17:39:59 +00:00
bootstage_accum(BOOTSTAGE_ID_ACCUM_FSP_S);
x86: fsp: Add FSP2 base support Add support for some important configuration options and FSP memory init. The memory init uses swizzle tables from the device tree. Support for the FSP_S binary is also included. Bootstage timing is used for both FSP_M and FSP_S and memory-mapped SPI reads. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-07 04:42:18 +00:00
if (ret)
return log_msg_ret("Silicon init fail\n", ret);
log_debug("done\n");
return 0;
}
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