2015-04-21 11:38:20 +00:00
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if ARCH_SOCFPGA
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2015-08-02 19:57:57 +00:00
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config TARGET_SOCFPGA_ARRIA5
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bool
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2015-12-02 19:31:25 +00:00
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select TARGET_SOCFPGA_GEN5
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2015-08-02 19:57:57 +00:00
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config TARGET_SOCFPGA_CYCLONE5
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bool
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2015-12-02 19:31:25 +00:00
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select TARGET_SOCFPGA_GEN5
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config TARGET_SOCFPGA_GEN5
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bool
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2015-08-02 19:57:57 +00:00
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2015-04-21 11:38:20 +00:00
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choice
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prompt "Altera SOCFPGA board select"
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2015-05-12 19:46:23 +00:00
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optional
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2015-04-21 11:38:20 +00:00
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2015-08-02 19:57:57 +00:00
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config TARGET_SOCFPGA_ARRIA5_SOCDK
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bool "Altera SOCFPGA SoCDK (Arria V)"
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select TARGET_SOCFPGA_ARRIA5
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2015-04-21 11:38:20 +00:00
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2015-08-02 19:57:57 +00:00
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config TARGET_SOCFPGA_CYCLONE5_SOCDK
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bool "Altera SOCFPGA SoCDK (Cyclone V)"
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select TARGET_SOCFPGA_CYCLONE5
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2015-04-21 11:38:20 +00:00
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2015-08-02 23:37:28 +00:00
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config TARGET_SOCFPGA_DENX_MCVEVK
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bool "DENX MCVEVK (Cyclone V)"
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select TARGET_SOCFPGA_CYCLONE5
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2015-11-23 16:06:27 +00:00
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config TARGET_SOCFPGA_EBV_SOCRATES
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bool "EBV SoCrates (Cyclone V)"
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select TARGET_SOCFPGA_CYCLONE5
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2016-06-07 10:37:23 +00:00
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config TARGET_SOCFPGA_IS1
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bool "IS1 (Cyclone V)"
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select TARGET_SOCFPGA_CYCLONE5
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2015-12-01 17:09:52 +00:00
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config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
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bool "samtec VIN|ING FPGA (Cyclone V)"
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select TARGET_SOCFPGA_CYCLONE5
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2016-06-08 00:57:05 +00:00
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config TARGET_SOCFPGA_SR1500
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bool "SR1500 (Cyclone V)"
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select TARGET_SOCFPGA_CYCLONE5
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2015-09-01 22:41:52 +00:00
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config TARGET_SOCFPGA_TERASIC_DE0_NANO
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bool "Terasic DE0-Nano-Atlas (Cyclone V)"
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select TARGET_SOCFPGA_CYCLONE5
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2015-06-21 15:28:53 +00:00
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config TARGET_SOCFPGA_TERASIC_SOCKIT
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bool "Terasic SoCkit (Cyclone V)"
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select TARGET_SOCFPGA_CYCLONE5
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2015-04-21 11:38:20 +00:00
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endchoice
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config SYS_BOARD
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2015-08-10 19:24:53 +00:00
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default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
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default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
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2015-09-01 22:41:52 +00:00
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default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
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2016-06-07 10:37:23 +00:00
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default "is1" if TARGET_SOCFPGA_IS1
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2015-08-02 23:37:28 +00:00
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default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
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2015-06-21 15:28:53 +00:00
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default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
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2015-11-23 16:06:27 +00:00
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default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
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2015-11-18 10:06:09 +00:00
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default "sr1500" if TARGET_SOCFPGA_SR1500
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2015-12-01 17:09:52 +00:00
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default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
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2015-04-21 11:38:20 +00:00
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config SYS_VENDOR
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2015-08-02 19:57:57 +00:00
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default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
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default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
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2015-08-02 23:37:28 +00:00
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default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
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2015-11-23 16:06:27 +00:00
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default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
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2015-12-01 17:09:52 +00:00
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default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
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2015-09-01 22:41:52 +00:00
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default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
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2015-06-21 15:28:53 +00:00
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default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
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2015-04-21 11:38:20 +00:00
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config SYS_SOC
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default "socfpga"
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config SYS_CONFIG_NAME
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2015-09-22 22:01:32 +00:00
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default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
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default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
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2015-09-01 22:41:52 +00:00
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default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
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2016-06-07 10:37:23 +00:00
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default "socfpga_is1" if TARGET_SOCFPGA_IS1
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2015-08-02 23:37:28 +00:00
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default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
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2015-06-21 15:28:53 +00:00
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default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
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2015-11-23 16:06:27 +00:00
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default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
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2015-11-18 10:06:09 +00:00
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default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
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2015-12-01 17:09:52 +00:00
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default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
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2015-04-21 11:38:20 +00:00
|
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endif
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