u-boot/arch/arm/include/asm/arch-omap5/i2c.h

/*
 * (C) Copyright 2004-2010
 * Texas Instruments, <www.ti.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#ifndef _OMAP5_I2C_H_
#define _OMAP5_I2C_H_

#define I2C_DEFAULT_BASE	I2C_BASE1

struct i2c {
	unsigned short revnb_lo;	/* 0x00 */
	unsigned short res1;
	unsigned short revnb_hi;	/* 0x04 */
	unsigned short res2[5];
	unsigned short sysc;		/* 0x10 */
	unsigned short res3[9];
	unsigned short irqstatus_raw;	/* 0x24 */
	unsigned short res4;
	unsigned short stat;		/* 0x28 */
	unsigned short res5;
	unsigned short ie;		/* 0x2C */
	unsigned short res6;
	unsigned short irqenable_clr;	/* 0x30 */
	unsigned short res7;
	unsigned short iv;		/* 0x34 */
	unsigned short res8[45];
	unsigned short syss;		/* 0x90 */
	unsigned short res9;
	unsigned short buf;		/* 0x94 */
	unsigned short res10;
	unsigned short cnt;		/* 0x98 */
	unsigned short res11;
	unsigned short data;		/* 0x9C */
	unsigned short res13;
	unsigned short res14;		/* 0xA0 */
	unsigned short res15;
	unsigned short con;		/* 0xA4 */
	unsigned short res16;
	unsigned short oa;		/* 0xA8 */
	unsigned short res17;
	unsigned short sa;		/* 0xAC */
	unsigned short res18;
	unsigned short psc;		/* 0xB0 */
	unsigned short res19;
	unsigned short scll;		/* 0xB4 */
	unsigned short res20;
	unsigned short sclh;		/* 0xB8 */
	unsigned short res21;
	unsigned short systest;		/* 0xBC */
	unsigned short res22;
	unsigned short bufstat;		/* 0xC0 */
	unsigned short res23;
};

#endif /* _OMAP5_I2C_H_ */
omap5: Add minimal support for omap5430. This patch adds the minimal support for OMAP5. The platform and machine specific headers and sources updated for OMAP5430. OMAP5430 is Texas Instrument's SOC based on ARM Cortex-A15 SMP architecture. It's a dual core SOC with GIC used for interrupt handling and SCU for cache coherency. Also moved some part of code from the basic platform support that can be made common for OMAP4/5. Rest is kept out seperately. The same approach is followed for clocks and emif support in the subsequent patches. Signed-off-by: sricharan <r.sricharan@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> 2011-11-15 14:49:55 +00:00			`/*`
			`* (C) Copyright 2004-2010`
			`* Texas Instruments, <www.ti.com>`
			`*`
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> 2013-07-08 07:37:19 +00:00			`* SPDX-License-Identifier: GPL-2.0+`
omap5: Add minimal support for omap5430. This patch adds the minimal support for OMAP5. The platform and machine specific headers and sources updated for OMAP5430. OMAP5430 is Texas Instrument's SOC based on ARM Cortex-A15 SMP architecture. It's a dual core SOC with GIC used for interrupt handling and SCU for cache coherency. Also moved some part of code from the basic platform support that can be made common for OMAP4/5. Rest is kept out seperately. The same approach is followed for clocks and emif support in the subsequent patches. Signed-off-by: sricharan <r.sricharan@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> 2011-11-15 14:49:55 +00:00			`*/`
			`#ifndef _OMAP5_I2C_H_`
			`#define _OMAP5_I2C_H_`

			`#define I2C_DEFAULT_BASE I2C_BASE1`

			`struct i2c {`
			`unsigned short revnb_lo; /* 0x00 */`
			`unsigned short res1;`
			`unsigned short revnb_hi; /* 0x04 */`
omap5/dra7: i2c: correct register offset for sync register The register offset of i2c_sysc offset is not correct as per omap5[1]/dra7[2] TRM, correct the offsets as per the documentation. [1] - http://www.ti.com/lit/pdf/swpu249 [2] - http://www.ti.com/lit/pdf/spruhz6 Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> 2016-07-18 09:40:57 +00:00			`unsigned short res2[5];`
			`unsigned short sysc; /* 0x10 */`
			`unsigned short res3[9];`
omap5: Add minimal support for omap5430. This patch adds the minimal support for OMAP5. The platform and machine specific headers and sources updated for OMAP5430. OMAP5430 is Texas Instrument's SOC based on ARM Cortex-A15 SMP architecture. It's a dual core SOC with GIC used for interrupt handling and SCU for cache coherency. Also moved some part of code from the basic platform support that can be made common for OMAP4/5. Rest is kept out seperately. The same approach is followed for clocks and emif support in the subsequent patches. Signed-off-by: sricharan <r.sricharan@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> 2011-11-15 14:49:55 +00:00			`unsigned short irqstatus_raw; /* 0x24 */`
			`unsigned short res4;`
			`unsigned short stat; /* 0x28 */`
			`unsigned short res5;`
			`unsigned short ie; /* 0x2C */`
			`unsigned short res6;`
			`unsigned short irqenable_clr; /* 0x30 */`
			`unsigned short res7;`
			`unsigned short iv; /* 0x34 */`
			`unsigned short res8[45];`
			`unsigned short syss; /* 0x90 */`
			`unsigned short res9;`
			`unsigned short buf; /* 0x94 */`
			`unsigned short res10;`
			`unsigned short cnt; /* 0x98 */`
			`unsigned short res11;`
			`unsigned short data; /* 0x9C */`
			`unsigned short res13;`
			`unsigned short res14; /* 0xA0 */`
			`unsigned short res15;`
			`unsigned short con; /* 0xA4 */`
			`unsigned short res16;`
			`unsigned short oa; /* 0xA8 */`
			`unsigned short res17;`
			`unsigned short sa; /* 0xAC */`
			`unsigned short res18;`
			`unsigned short psc; /* 0xB0 */`
			`unsigned short res19;`
			`unsigned short scll; /* 0xB4 */`
			`unsigned short res20;`
			`unsigned short sclh; /* 0xB8 */`
			`unsigned short res21;`
			`unsigned short systest; /* 0xBC */`
			`unsigned short res22;`
			`unsigned short bufstat; /* 0xC0 */`
			`unsigned short res23;`
			`};`

			`#endif /* _OMAP5_I2C_H_ */`