mirror of
https://github.com/AsahiLinux/u-boot
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78 lines
2.3 KiB
C
78 lines
2.3 KiB
C
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/*
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* (C) Copyright 2006
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <ppc440.h>
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/*************************************************************************
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*
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* initdram -- 440EPx's DDR controller is a DENALI Core
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*
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************************************************************************/
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long int initdram (int board_type)
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{
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#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
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volatile ulong val;
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mtsdram(DDR0_02, 0x00000000);
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mtsdram(DDR0_00, 0x0000190A);
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mtsdram(DDR0_01, 0x01000000);
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mtsdram(DDR0_03, 0x02030602);
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mtsdram(DDR0_04, 0x13030300);
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mtsdram(DDR0_05, 0x0202050E);
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mtsdram(DDR0_06, 0x0104C823);
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mtsdram(DDR0_07, 0x000D0100);
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mtsdram(DDR0_08, 0x02360001);
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mtsdram(DDR0_09, 0x00011D5F);
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mtsdram(DDR0_10, 0x00000300);
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mtsdram(DDR0_11, 0x0027C800);
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mtsdram(DDR0_12, 0x00000003);
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mtsdram(DDR0_14, 0x00000000);
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mtsdram(DDR0_17, 0x19000000);
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mtsdram(DDR0_18, 0x19191919);
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mtsdram(DDR0_19, 0x19191919);
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mtsdram(DDR0_20, 0x0B0B0B0B);
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mtsdram(DDR0_21, 0x0B0B0B0B);
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mtsdram(DDR0_22, 0x00267F0B);
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mtsdram(DDR0_23, 0x00000000);
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mtsdram(DDR0_24, 0x01010002);
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mtsdram(DDR0_26, 0x5B260181);
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mtsdram(DDR0_27, 0x0000682B);
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mtsdram(DDR0_28, 0x00000000);
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mtsdram(DDR0_31, 0x00000000);
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mtsdram(DDR0_42, 0x01000006);
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mtsdram(DDR0_43, 0x050A0200);
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mtsdram(DDR0_44, 0x00000005);
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mtsdram(DDR0_02, 0x00000001);
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/*
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* Wait for DCC master delay line to finish calibration
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*/
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mfsdram(DDR0_17, val);
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while (((val >> 8) & 0x000007f) == 0) {
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mfsdram(DDR0_17, val);
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}
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#endif /* #ifndef CONFIG_NAND_U_BOOT */
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return (CFG_MBYTES_SDRAM << 20);
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}
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