u-boot/arch/arm/dts/imx8mm-venice.dts

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2021 Gateworks Corporation
 */

/dts-v1/;

#include "imx8mm.dtsi"

/ {
	model = "Gateworks Venice i.MX8MM board";
	compatible = "gw,imx8mm-venice", "fsl,imx8mm";

	chosen {
		stdout-path = &uart2;
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0x0 0x40000000 0 0x80000000>;
	};
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	eeprom@51 {
		compatible = "atmel,24c02";
		reg = <0x51>;
		pagesize = <16>;
	};
};

&i2c2 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	eeprom@52 {
		compatible = "atmel,24c32";
		reg = <0x52>;
		pagesize = <32>;
	};
};

/* console */
&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
};

/* eMMC */
&usdhc3 {
	assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
	assigned-clock-rates = <400000000>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};

&iomuxc {
	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3
			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3
			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x190
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d0
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d0
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d0
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d0
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d0
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d0
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d0
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d0
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d0
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x190
		>;
	};

	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x194
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d4
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d4
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d4
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x194
		>;
	};

	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x196
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d6
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d6
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d6
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d6
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d6
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d6
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d6
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d6
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d6
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x196
		>;
	};

	pinctrl_wdog: wdoggrp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
		>;
	};
};