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u-boot/board/ti/dra7xx/mux_data.h

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arm: dra7xx: Add board files for DRA7XX socs Adding new board files for DRA7XX socs. The pad registers layout is changed completely from OMAP5 So introducing the new structure here and also adding the minimal data. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishant Kamat <nskamat@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com> [trini: Adapt omap_mmc_init call for last 2 params] Signed-off-by: Tom Rini <trini@ti.com>
2013-02-12 21:29:08 +00:00
/*
* (C) Copyright 2013
* Texas Instruments Incorporated, <www.ti.com>
*
* Sricharan R <r.sricharan@ti.com>
* Nishant Kamat <nskamat@ti.com>
*
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
2013-07-08 07:37:19 +00:00
* SPDX-License-Identifier: GPL-2.0+
arm: dra7xx: Add board files for DRA7XX socs Adding new board files for DRA7XX socs. The pad registers layout is changed completely from OMAP5 So introducing the new structure here and also adding the minimal data. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishant Kamat <nskamat@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com> [trini: Adapt omap_mmc_init call for last 2 params] Signed-off-by: Tom Rini <trini@ti.com>
2013-02-12 21:29:08 +00:00
*/
#ifndef _MUX_DATA_DRA7XX_H_
#define _MUX_DATA_DRA7XX_H_
#include <asm/arch/mux_dra7xx.h>
const struct pad_conf_entry core_padconf_array_essential[] = {
ARM: DRA7xx: Update pinmux data Updating pinmux data as specified in the latest DM Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Balaji T K <balajitk@ti.com>
2013-05-30 03:19:37 +00:00
{MMC1_CLK, (IEN | PTU | PDIS | M0)}, /* MMC1_CLK */
{MMC1_CMD, (IEN | PTU | PDIS | M0)}, /* MMC1_CMD */
{MMC1_DAT0, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT0 */
{MMC1_DAT1, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT1 */
{MMC1_DAT2, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT2 */
{MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */
{MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */
{MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */
board/ti/dra7xx: add support for parallel NOR This patch adds support for parallel NOR device (S29GL512S10) present on J6-EVM. The Flash device is connected to GPMC controller on chip-select[0] and accessed as memory-mapped device. It has data-witdh=x16, capacity-64MBytes(512Mbits) and is CFI compatible. As multiple devices are share GPMC pins on this board, so following board settings are required to detect NOR device: SW5.1 (NAND_BOOTn) = OFF (logic-1) SW5.2 (NOR_BOOTn) = ON (logic-0) /* Active-low */ SW5.3 (eMMC_BOOTn) = OFF (logic-1) SW5.4 (QSPI_BOOTn) = OFF (logic-1) And also set appropriate SYSBOOT configurations: SW3.1 (SYSBOOT[ 8])= ON (logic-1) /* selects SYS_CLK1 speed */ SW3.2 (SYSBOOT[ 9])= OFF (logic-0) /* selects SYS_CLK1 speed */ SW3.3 (SYSBOOT[10])= ON (logic-1) /* wait-pin monitoring = enabled */ SW3.4 (SYSBOOT[11])= OFF (logic-0) /* device type: Non Muxed */ SW3.5 (SYSBOOT[12])= OFF (logic-0) /* device type: Non Muxed */ SW3.6 (SYSBOOT[13])= ON (logic-1) /* device bus-width: 1(x16) */ SW3.7 (SYSBOOT[14])= OFF (logic-0) /* reserved */ SW3.8 (SYSBOOT[15])= ON (logic-1) /* reserved */ Also, following changes are required to enable NOR Flash support in dra7xx_evm board profile:
2014-07-22 10:33:24 +00:00
#if defined(CONFIG_NOR)
/* NOR only pin-mux */
{GPMC_A0 , M0 | IDIS | PDIS}, /* nor.GPMC_A[0 ] */
{GPMC_A1 , M0 | IDIS | PDIS}, /* nor.GPMC_A[1 ] */
{GPMC_A2 , M0 | IDIS | PDIS}, /* nor.GPMC_A[2 ] */
{GPMC_A3 , M0 | IDIS | PDIS}, /* nor.GPMC_A[3 ] */
{GPMC_A4 , M0 | IDIS | PDIS}, /* nor.GPMC_A[4 ] */
{GPMC_A5 , M0 | IDIS | PDIS}, /* nor.GPMC_A[5 ] */
{GPMC_A6 , M0 | IDIS | PDIS}, /* nor.GPMC_A[6 ] */
{GPMC_A7 , M0 | IDIS | PDIS}, /* nor.GPMC_A[7 ] */
{GPMC_A8 , M0 | IDIS | PDIS}, /* nor.GPMC_A[8 ] */
{GPMC_A9 , M0 | IDIS | PDIS}, /* nor.GPMC_A[9 ] */
{GPMC_A10 , M0 | IDIS | PDIS}, /* nor.GPMC_A[10] */
{GPMC_A11 , M0 | IDIS | PDIS}, /* nor.GPMC_A[11] */
{GPMC_A12 , M0 | IDIS | PDIS}, /* nor.GPMC_A[12] */
{GPMC_A13 , M0 | IDIS | PDIS}, /* nor.GPMC_A[13] */
{GPMC_A14 , M0 | IDIS | PDIS}, /* nor.GPMC_A[14] */
{GPMC_A15 , M0 | IDIS | PDIS}, /* nor.GPMC_A[15] */
{GPMC_A16 , M0 | IDIS | PDIS}, /* nor.GPMC_A[16] */
{GPMC_A17 , M0 | IDIS | PDIS}, /* nor.GPMC_A[17] */
{GPMC_A18 , M0 | IDIS | PDIS}, /* nor.GPMC_A[18] */
{GPMC_A19 , M0 | IDIS | PDIS}, /* nor.GPMC_A[19] */
{GPMC_A20 , M0 | IDIS | PDIS}, /* nor.GPMC_A[20] */
{GPMC_A21 , M0 | IDIS | PDIS}, /* nor.GPMC_A[21] */
{GPMC_A22 , M0 | IDIS | PDIS}, /* nor.GPMC_A[22] */
{GPMC_A23 , M0 | IDIS | PDIS}, /* nor.GPMC_A[23] */
{GPMC_A24 , M0 | IDIS | PDIS}, /* nor.GPMC_A[24] */
{GPMC_A25 , M0 | IDIS | PDIS}, /* nor.GPMC_A[25] */
{GPMC_A26 , M0 | IDIS | PDIS}, /* nor.GPMC_A[26] */
#else
/* eMMC pinmux */
ARM: DRA7xx: Update pinmux data Updating pinmux data as specified in the latest DM Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Balaji T K <balajitk@ti.com>
2013-05-30 03:19:37 +00:00
{GPMC_A19, (IEN | PTU | PDIS | M1)}, /* mmc2_dat4 */
{GPMC_A20, (IEN | PTU | PDIS | M1)}, /* mmc2_dat5 */
{GPMC_A21, (IEN | PTU | PDIS | M1)}, /* mmc2_dat6 */
{GPMC_A22, (IEN | PTU | PDIS | M1)}, /* mmc2_dat7 */
{GPMC_A23, (IEN | PTU | PDIS | M1)}, /* mmc2_clk */
{GPMC_A24, (IEN | PTU | PDIS | M1)}, /* mmc2_dat0 */
{GPMC_A25, (IEN | PTU | PDIS | M1)}, /* mmc2_dat1 */
{GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */
{GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */
{GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */
board/ti/dra7xx: add support for parallel NOR This patch adds support for parallel NOR device (S29GL512S10) present on J6-EVM. The Flash device is connected to GPMC controller on chip-select[0] and accessed as memory-mapped device. It has data-witdh=x16, capacity-64MBytes(512Mbits) and is CFI compatible. As multiple devices are share GPMC pins on this board, so following board settings are required to detect NOR device: SW5.1 (NAND_BOOTn) = OFF (logic-1) SW5.2 (NOR_BOOTn) = ON (logic-0) /* Active-low */ SW5.3 (eMMC_BOOTn) = OFF (logic-1) SW5.4 (QSPI_BOOTn) = OFF (logic-1) And also set appropriate SYSBOOT configurations: SW3.1 (SYSBOOT[ 8])= ON (logic-1) /* selects SYS_CLK1 speed */ SW3.2 (SYSBOOT[ 9])= OFF (logic-0) /* selects SYS_CLK1 speed */ SW3.3 (SYSBOOT[10])= ON (logic-1) /* wait-pin monitoring = enabled */ SW3.4 (SYSBOOT[11])= OFF (logic-0) /* device type: Non Muxed */ SW3.5 (SYSBOOT[12])= OFF (logic-0) /* device type: Non Muxed */ SW3.6 (SYSBOOT[13])= ON (logic-1) /* device bus-width: 1(x16) */ SW3.7 (SYSBOOT[14])= OFF (logic-0) /* reserved */ SW3.8 (SYSBOOT[15])= ON (logic-1) /* reserved */ Also, following changes are required to enable NOR Flash support in dra7xx_evm board profile:
2014-07-22 10:33:24 +00:00
#endif
board: ti: dra7xx: add mux data for UART3 J6 EVM can be built with UART3 as console, but currently there's nothing muxing UART3 correctly. Likely this only works because, based on commit log, author was only testing with UART3 boot and - I assume - ROM code leave UART3 correctly muxed in that case. If we want to boot from MMC and still use UART3 as console, then we need to mux those signals correctly. Signed-off-by: Felipe Balbi <balbi@ti.com>
2014-06-26 21:38:05 +00:00
#if (CONFIG_CONS_INDEX == 1)
ARM: DRA7xx: Update pinmux data Updating pinmux data as specified in the latest DM Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Balaji T K <balajitk@ti.com>
2013-05-30 03:19:37 +00:00
{UART1_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_RXD */
{UART1_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_TXD */
{UART1_CTSN, (IEN | PTU | PDIS | M3)}, /* UART1_CTSN */
{UART1_RTSN, (IEN | PTU | PDIS | M3)}, /* UART1_RTSN */
board: ti: dra7xx: add mux data for UART3 J6 EVM can be built with UART3 as console, but currently there's nothing muxing UART3 correctly. Likely this only works because, based on commit log, author was only testing with UART3 boot and - I assume - ROM code leave UART3 correctly muxed in that case. If we want to boot from MMC and still use UART3 as console, then we need to mux those signals correctly. Signed-off-by: Felipe Balbi <balbi@ti.com>
2014-06-26 21:38:05 +00:00
#elif (CONFIG_CONS_INDEX == 3)
{UART3_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_RXD */
{UART3_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_TXD */
#endif
ARM: DRA7xx: Update pinmux data Updating pinmux data as specified in the latest DM Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Balaji T K <balajitk@ti.com>
2013-05-30 03:19:37 +00:00
{I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */
{I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */
ARM: DRA7xx: Add CPSW and MDIO pinmux support Adding CPSW Slave 0 and MDIO pinmux support for DRA7xx EVM Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2013-07-08 10:34:42 +00:00
{MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */
{MDIO_D, (IEN | PTU | PEN | M0)}, /* MDIO_D */
{RGMII0_TXC, (M0) },
{RGMII0_TXCTL, (M0) },
{RGMII0_TXD3, (M0) },
{RGMII0_TXD2, (M0) },
{RGMII0_TXD1, (M0) },
{RGMII0_TXD0, (M0) },
{RGMII0_RXC, (IEN | M0) },
{RGMII0_RXCTL, (IEN | M0) },
{RGMII0_RXD3, (IEN | M0) },
{RGMII0_RXD2, (IEN | M0) },
{RGMII0_RXD1, (IEN | M0) },
{RGMII0_RXD0, (IEN | M0) },
ARM: DRA7xx: Add cpsw second port pinmux Add cpsw second slave port pinmux to use it as primary ethernet port Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2014-05-22 09:07:11 +00:00
{VIN2A_D12, (M3) },
{VIN2A_D13, (M3) },
{VIN2A_D14, (M3) },
{VIN2A_D15, (M3) },
{VIN2A_D16, (M3) },
{VIN2A_D17, (M3) },
{VIN2A_D18, (IEN | M3)},
{VIN2A_D19, (IEN | M3)},
{VIN2A_D20, (IEN | M3)},
{VIN2A_D21, (IEN | M3)},
{VIN2A_D22, (IEN | M3)},
{VIN2A_D23, (IEN | M3)},
board/ti/dra7xx: add support for parallel NOR This patch adds support for parallel NOR device (S29GL512S10) present on J6-EVM. The Flash device is connected to GPMC controller on chip-select[0] and accessed as memory-mapped device. It has data-witdh=x16, capacity-64MBytes(512Mbits) and is CFI compatible. As multiple devices are share GPMC pins on this board, so following board settings are required to detect NOR device: SW5.1 (NAND_BOOTn) = OFF (logic-1) SW5.2 (NOR_BOOTn) = ON (logic-0) /* Active-low */ SW5.3 (eMMC_BOOTn) = OFF (logic-1) SW5.4 (QSPI_BOOTn) = OFF (logic-1) And also set appropriate SYSBOOT configurations: SW3.1 (SYSBOOT[ 8])= ON (logic-1) /* selects SYS_CLK1 speed */ SW3.2 (SYSBOOT[ 9])= OFF (logic-0) /* selects SYS_CLK1 speed */ SW3.3 (SYSBOOT[10])= ON (logic-1) /* wait-pin monitoring = enabled */ SW3.4 (SYSBOOT[11])= OFF (logic-0) /* device type: Non Muxed */ SW3.5 (SYSBOOT[12])= OFF (logic-0) /* device type: Non Muxed */ SW3.6 (SYSBOOT[13])= ON (logic-1) /* device bus-width: 1(x16) */ SW3.7 (SYSBOOT[14])= OFF (logic-0) /* reserved */ SW3.8 (SYSBOOT[15])= ON (logic-1) /* reserved */ Also, following changes are required to enable NOR Flash support in dra7xx_evm board profile:
2014-07-22 10:33:24 +00:00
#if defined(CONFIG_NAND) || defined(CONFIG_NOR)
board/ti/dra7xx: add support for parallel NAND This patch adds support for x16 NAND device (MT29F2G16AAD) connected to GPMC chip-select[0] on DRA7xx EVM. As GPMC pins are shared by multiple devices, so in addition to this patch following board settings are required for NAND device detection [1]: SW5.9 (GPMC_WPN) = OFF (logic-1) SW5.1 (NAND_BOOTn) = ON (logic-0) /* Active-low */ SW5.2 (NOR_BOOTn) = OFF (logic-1) SW5.3 (eMMC_BOOTn) = OFF (logic-1) SW5.4 (QSPI_BOOTn) = OFF (logic-1) And also set appropriate SYSBOOT configurations SW2.1 (SYSBOOT[0]) = ON (logic-1) /* selects NAND Boot */ SW2.2 (SYSBOOT[1]) = OFF (logic-0) /* selects NAND Boot */ SW2.3 (SYSBOOT[2]) = OFF (logic-0) /* selects NAND Boot */ SW2.4 (SYSBOOT[3]) = OFF (logic-0) /* selects NAND Boot */ SW2.5 (SYSBOOT[4]) = ON (logic-1) /* selects NAND Boot */ SW2.6 (SYSBOOT[5]) = ON (logic-1) /* selects NAND Boot */ SW2.7 (SYSBOOT[6]) = OFF (logic-0) /* reserved */ SW2.8 (SYSBOOT[7]) = OFF (logic-0) /* reserved */ SW3.1 (SYSBOOT[ 8])= ON (logic-1) /* selects SYS_CLK1 speed */ SW3.2 (SYSBOOT[ 9])= OFF (logic-0) /* selects SYS_CLK1 speed */ SW3.3 (SYSBOOT[10])= ON (logic-1) /* wait-pin monitoring = enabled */ SW3.4 (SYSBOOT[11])= OFF (logic-0) /* device type: Addr/Data Muxed */ SW3.5 (SYSBOOT[12])= ON (logic-1) /* device type: Addr/Data Muxed */ SW3.6 (SYSBOOT[13])= ON (logic-1) /* device bus-width: 1(x16) */ SW3.7 (SYSBOOT[14])= OFF (logic-0) /* reserved */ SW3.8 (SYSBOOT[15])= ON (logic-1) /* reserved */ Following changes are required in board.cfg to enable NAND on J6-EVM:
2014-07-22 10:33:23 +00:00
/* NAND / NOR pin-mux */
{GPMC_AD0 , M0 | IEN | PDIS}, /* GPMC_AD0 */
{GPMC_AD1 , M0 | IEN | PDIS}, /* GPMC_AD1 */
{GPMC_AD2 , M0 | IEN | PDIS}, /* GPMC_AD2 */
{GPMC_AD3 , M0 | IEN | PDIS}, /* GPMC_AD3 */
{GPMC_AD4 , M0 | IEN | PDIS}, /* GPMC_AD4 */
{GPMC_AD5 , M0 | IEN | PDIS}, /* GPMC_AD5 */
{GPMC_AD6 , M0 | IEN | PDIS}, /* GPMC_AD6 */
{GPMC_AD7 , M0 | IEN | PDIS}, /* GPMC_AD7 */
{GPMC_AD8 , M0 | IEN | PDIS}, /* GPMC_AD8 */
{GPMC_AD9 , M0 | IEN | PDIS}, /* GPMC_AD9 */
{GPMC_AD10, M0 | IEN | PDIS}, /* GPMC_AD10 */
{GPMC_AD11, M0 | IEN | PDIS}, /* GPMC_AD11 */
{GPMC_AD12, M0 | IEN | PDIS}, /* GPMC_AD12 */
{GPMC_AD13, M0 | IEN | PDIS}, /* GPMC_AD13 */
{GPMC_AD14, M0 | IEN | PDIS}, /* GPMC_AD14 */
{GPMC_AD15, M0 | IEN | PDIS}, /* GPMC_AD15 */
{GPMC_CS0, M0 | IDIS | PEN | PTU}, /* GPMC chip-select */
{GPMC_ADVN_ALE, M0 | IDIS | PEN | PTD}, /* GPMC Addr latch */
{GPMC_OEN_REN, M0 | IDIS | PEN | PTU}, /* GPMC Read enable */
{GPMC_WEN, M0 | IDIS | PEN | PTU}, /* GPMC Write enable_n */
{GPMC_BEN0, M0 | IDIS | PEN | PTD}, /* GPMC Byte/Column En */
{GPMC_WAIT0, M0 | IEN | PEN | PTU}, /* GPMC Wait/Ready */
/* GPMC_WPN (Write Protect) is controlled by DIP Switch SW10(12) */
#else
/* QSPI pin-mux */
dra7xx_evm: add SPL API, QSPI, and serial flash support Enables support for SPI SPL, QSPI and Spansion serial flash device on the EVM. Configures pin muxes for QSPI mode. Signed-off-by: Matt Porter <matt.porter@linaro.org> Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2013-10-07 10:23:03 +00:00
{GPMC_A13, (IEN | PDIS | M1)}, /* QSPI1_RTCLK */
{GPMC_A14, (IEN | PDIS | M1)}, /* QSPI1_D[3] */
{GPMC_A15, (IEN | PDIS | M1)}, /* QSPI1_D[2] */
{GPMC_A16, (IEN | PDIS | M1)}, /* QSPI1_D[1] */
{GPMC_A17, (IEN | PDIS | M1)}, /* QSPI1_D[0] */
{GPMC_A18, (M1)}, /* QSPI1_SCLK */
{GPMC_A3, (IEN | PDIS | M1)}, /* QSPI1_CS2 */
{GPMC_A4, (IEN | PDIS | M1)}, /* QSPI1_CS3 */
{GPMC_CS2, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS0 */
{GPMC_CS3, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS1*/
board/ti/dra7xx: add support for parallel NOR This patch adds support for parallel NOR device (S29GL512S10) present on J6-EVM. The Flash device is connected to GPMC controller on chip-select[0] and accessed as memory-mapped device. It has data-witdh=x16, capacity-64MBytes(512Mbits) and is CFI compatible. As multiple devices are share GPMC pins on this board, so following board settings are required to detect NOR device: SW5.1 (NAND_BOOTn) = OFF (logic-1) SW5.2 (NOR_BOOTn) = ON (logic-0) /* Active-low */ SW5.3 (eMMC_BOOTn) = OFF (logic-1) SW5.4 (QSPI_BOOTn) = OFF (logic-1) And also set appropriate SYSBOOT configurations: SW3.1 (SYSBOOT[ 8])= ON (logic-1) /* selects SYS_CLK1 speed */ SW3.2 (SYSBOOT[ 9])= OFF (logic-0) /* selects SYS_CLK1 speed */ SW3.3 (SYSBOOT[10])= ON (logic-1) /* wait-pin monitoring = enabled */ SW3.4 (SYSBOOT[11])= OFF (logic-0) /* device type: Non Muxed */ SW3.5 (SYSBOOT[12])= OFF (logic-0) /* device type: Non Muxed */ SW3.6 (SYSBOOT[13])= ON (logic-1) /* device bus-width: 1(x16) */ SW3.7 (SYSBOOT[14])= OFF (logic-0) /* reserved */ SW3.8 (SYSBOOT[15])= ON (logic-1) /* reserved */ Also, following changes are required to enable NOR Flash support in dra7xx_evm board profile:
2014-07-22 10:33:24 +00:00
#endif /* CONFIG_NAND || CONFIG_NOR */
usb: dra7xx: Add support for dra7xx xhci USB host Add the support for the dra7xx xhci usb host. dra7xx does not contain an EHCI controller so the headers can be removed from the board file. The xHCI host on dra7xx is connected to a usb2 phy so need to add support to enable those clocks. Signed-off-by: Dan Murphy <dmurphy@ti.com>
2013-10-11 17:28:17 +00:00
{USB2_DRVVBUS, (M0 | IEN | FSC) },
ARM: DRA: Enable VTT regulator DRA7 evm REV G and later boards uses a vtt regulator for DDR3 termination and this is controlled by gpio7_11. Configuring gpio7_11. The pad A22(offset 0x3b4) is used by gpio7_11 on REV G and later boards, and left unused on previous boards, so it is safe enough to enable gpio on all DRA7 boards. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2014-08-04 14:12:24 +00:00
{SPI1_CS1, (PEN | IDIS | M14) },
arm: dra7xx: Add board files for DRA7XX socs Adding new board files for DRA7XX socs. The pad registers layout is changed completely from OMAP5 So introducing the new structure here and also adding the minimal data. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishant Kamat <nskamat@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com> [trini: Adapt omap_mmc_init call for last 2 params] Signed-off-by: Tom Rini <trini@ti.com>
2013-02-12 21:29:08 +00:00
};
#endif /* _MUX_DATA_DRA7XX_H_ */
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