2018-09-28 12:50:53 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2016-2018 ARM Ltd.
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* Author: Liviu Dudau <liviu.dudau@foss.arm.com>
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*
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*/
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#define DEBUG
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#include <common.h>
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2020-02-03 14:36:16 +00:00
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#include <malloc.h>
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2018-09-28 12:50:53 +00:00
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#include <video.h>
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#include <dm.h>
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#ifdef CONFIG_DISPLAY
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#include <display.h>
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#endif
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#include <fdtdec.h>
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#include <asm/io.h>
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#include <os.h>
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#include <fdt_support.h>
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#include <clk.h>
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2020-02-03 14:36:16 +00:00
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#include <dm/device_compat.h>
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2020-05-10 17:40:11 +00:00
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#include <linux/delay.h>
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2018-09-28 12:50:53 +00:00
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#include <linux/sizes.h>
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#define MALIDP_CORE_ID 0x0018
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#define MALIDP_REG_BG_COLOR 0x0044
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#define MALIDP_LAYER_LV1 0x0100
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#define MALIDP_DC_STATUS 0xc000
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#define MALIDP_DC_CONTROL 0xc010
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#define MALIDP_DC_CFG_VALID 0xc014
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/* offsets inside the modesetting register block */
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#define MALIDP_H_INTERVALS 0x0000
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#define MALIDP_V_INTERVALS 0x0004
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#define MALIDP_SYNC_CONTROL 0x0008
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#define MALIDP_HV_ACTIVESIZE 0x000c
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#define MALIDP_OUTPUT_DEPTH 0x001c
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/* offsets inside the layer register block */
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#define MALIDP_LAYER_FORMAT 0x0000
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#define MALIDP_LAYER_CONTROL 0x0004
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#define MALIDP_LAYER_IN_SIZE 0x000c
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#define MALIDP_LAYER_CMP_SIZE 0x0010
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#define MALIDP_LAYER_STRIDE 0x0018
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#define MALIDP_LAYER_PTR_LOW 0x0024
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#define MALIDP_LAYER_PTR_HIGH 0x0028
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/* offsets inside the IRQ control blocks */
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#define MALIDP_REG_MASKIRQ 0x0008
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#define MALIDP_REG_CLEARIRQ 0x000c
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#define M1BITS 0x0001
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#define M2BITS 0x0003
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#define M4BITS 0x000f
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#define M8BITS 0x00ff
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#define M10BITS 0x03ff
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#define M12BITS 0x0fff
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#define M13BITS 0x1fff
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#define M16BITS 0xffff
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#define M17BITS 0x1ffff
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#define MALIDP_H_FRONTPORCH(x) (((x) & M12BITS) << 0)
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#define MALIDP_H_BACKPORCH(x) (((x) & M10BITS) << 16)
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#define MALIDP_V_FRONTPORCH(x) (((x) & M12BITS) << 0)
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#define MALIDP_V_BACKPORCH(x) (((x) & M8BITS) << 16)
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#define MALIDP_H_SYNCWIDTH(x) (((x) & M10BITS) << 0)
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#define MALIDP_V_SYNCWIDTH(x) (((x) & M8BITS) << 16)
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#define MALIDP_H_ACTIVE(x) (((x) & M13BITS) << 0)
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#define MALIDP_V_ACTIVE(x) (((x) & M13BITS) << 16)
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#define MALIDP_CMP_V_SIZE(x) (((x) & M13BITS) << 16)
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#define MALIDP_CMP_H_SIZE(x) (((x) & M13BITS) << 0)
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#define MALIDP_IN_V_SIZE(x) (((x) & M13BITS) << 16)
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#define MALIDP_IN_H_SIZE(x) (((x) & M13BITS) << 0)
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#define MALIDP_DC_CM_CONTROL(x) ((x) & M1BITS) << 16, 1 << 16
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#define MALIDP_DC_STATUS_GET_CM(reg) (((reg) >> 16) & M1BITS)
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#define MALIDP_FORMAT_ARGB8888 0x08
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#define MALIDP_DEFAULT_BG_R 0x0
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#define MALIDP_DEFAULT_BG_G 0x0
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#define MALIDP_DEFAULT_BG_B 0x0
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#define MALIDP_PRODUCT_ID(core_id) ((u32)(core_id) >> 16)
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#define MALIDP500 0x500
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DECLARE_GLOBAL_DATA_PTR;
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struct malidp_priv {
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phys_addr_t base_addr;
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phys_addr_t dc_status_addr;
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phys_addr_t dc_control_addr;
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phys_addr_t cval_addr;
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struct udevice *display; /* display device attached */
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struct clk aclk;
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struct clk pxlclk;
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u16 modeset_regs_offset;
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u8 config_bit_shift;
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u8 clear_irq; /* offset for IRQ clear register */
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};
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static const struct video_ops malidp_ops = {
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};
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static int malidp_get_hwid(phys_addr_t base_addr)
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{
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int hwid;
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/*
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* reading from the old CORE_ID offset will always
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* return 0x5000000 on DP500
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*/
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hwid = readl(base_addr + MALIDP_CORE_ID);
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if (MALIDP_PRODUCT_ID(hwid) == MALIDP500)
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return hwid;
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/* otherwise try the other gen CORE_ID offset */
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hwid = readl(base_addr + MALIDP_DC_STATUS + MALIDP_CORE_ID);
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return hwid;
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}
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/*
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* wait for config mode bit setup to be acted upon by the hardware
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*/
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static int malidp_wait_configdone(struct malidp_priv *malidp)
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{
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u32 status, tries = 300;
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while (tries--) {
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status = readl(malidp->dc_status_addr);
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if ((status >> malidp->config_bit_shift) & 1)
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break;
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udelay(500);
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}
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if (!tries)
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return -ETIMEDOUT;
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return 0;
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}
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/*
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* signal the hardware to enter configuration mode
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*/
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static int malidp_enter_config(struct malidp_priv *malidp)
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{
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setbits_le32(malidp->dc_control_addr, 1 << malidp->config_bit_shift);
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return malidp_wait_configdone(malidp);
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}
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/*
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* signal the hardware to exit configuration mode
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*/
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static int malidp_leave_config(struct malidp_priv *malidp)
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{
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clrbits_le32(malidp->dc_control_addr, 1 << malidp->config_bit_shift);
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return malidp_wait_configdone(malidp);
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}
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static void malidp_setup_timings(struct malidp_priv *malidp,
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struct display_timing *timings)
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{
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u32 val = MALIDP_H_SYNCWIDTH(timings->hsync_len.typ) |
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MALIDP_V_SYNCWIDTH(timings->vsync_len.typ);
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writel(val, malidp->base_addr + malidp->modeset_regs_offset +
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MALIDP_SYNC_CONTROL);
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val = MALIDP_H_BACKPORCH(timings->hback_porch.typ) |
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MALIDP_H_FRONTPORCH(timings->hfront_porch.typ);
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writel(val, malidp->base_addr + malidp->modeset_regs_offset +
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MALIDP_H_INTERVALS);
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val = MALIDP_V_BACKPORCH(timings->vback_porch.typ) |
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MALIDP_V_FRONTPORCH(timings->vfront_porch.typ);
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writel(val, malidp->base_addr + malidp->modeset_regs_offset +
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MALIDP_V_INTERVALS);
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val = MALIDP_H_ACTIVE(timings->hactive.typ) |
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MALIDP_V_ACTIVE(timings->vactive.typ);
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writel(val, malidp->base_addr + malidp->modeset_regs_offset +
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MALIDP_HV_ACTIVESIZE);
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/* default output bit-depth per colour is 8 bits */
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writel(0x080808, malidp->base_addr + malidp->modeset_regs_offset +
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MALIDP_OUTPUT_DEPTH);
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}
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static int malidp_setup_mode(struct malidp_priv *malidp,
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struct display_timing *timings)
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{
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int err;
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if (clk_set_rate(&malidp->pxlclk, timings->pixelclock.typ) == 0)
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return -EIO;
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malidp_setup_timings(malidp, timings);
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err = display_enable(malidp->display, 8, timings);
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if (err)
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printf("display_enable failed with %d\n", err);
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return err;
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}
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static void malidp_setup_layer(struct malidp_priv *malidp,
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struct display_timing *timings,
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u32 layer_offset, phys_addr_t fb_addr)
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{
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u32 val;
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/* setup the base layer's pixel format to A8R8G8B8 */
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writel(MALIDP_FORMAT_ARGB8888, malidp->base_addr + layer_offset +
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MALIDP_LAYER_FORMAT);
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/* setup layer composition size */
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val = MALIDP_CMP_V_SIZE(timings->vactive.typ) |
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MALIDP_CMP_H_SIZE(timings->hactive.typ);
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writel(val, malidp->base_addr + layer_offset +
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MALIDP_LAYER_CMP_SIZE);
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/* setup layer input size */
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val = MALIDP_IN_V_SIZE(timings->vactive.typ) |
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MALIDP_IN_H_SIZE(timings->hactive.typ);
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writel(val, malidp->base_addr + layer_offset + MALIDP_LAYER_IN_SIZE);
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/* setup layer stride in bytes */
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writel(timings->hactive.typ << 2, malidp->base_addr + layer_offset +
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MALIDP_LAYER_STRIDE);
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/* set framebuffer address */
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writel(lower_32_bits(fb_addr), malidp->base_addr + layer_offset +
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MALIDP_LAYER_PTR_LOW);
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writel(upper_32_bits(fb_addr), malidp->base_addr + layer_offset +
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MALIDP_LAYER_PTR_HIGH);
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/* enable layer */
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setbits_le32(malidp->base_addr + layer_offset +
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MALIDP_LAYER_CONTROL, 1);
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}
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static void malidp_set_configvalid(struct malidp_priv *malidp)
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{
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setbits_le32(malidp->cval_addr, 1);
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}
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static int malidp_update_timings_from_edid(struct udevice *dev,
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struct display_timing *timings)
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{
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#ifdef CONFIG_DISPLAY
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struct malidp_priv *priv = dev_get_priv(dev);
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struct udevice *disp_dev;
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int err;
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err = uclass_first_device(UCLASS_DISPLAY, &disp_dev);
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if (err)
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return err;
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priv->display = disp_dev;
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err = display_read_timing(disp_dev, timings);
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if (err)
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return err;
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#endif
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return 0;
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}
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static int malidp_probe(struct udevice *dev)
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{
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struct video_priv *uc_priv = dev_get_uclass_priv(dev);
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struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
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ofnode framebuffer = ofnode_find_subnode(dev_ofnode(dev), "framebuffer");
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struct malidp_priv *priv = dev_get_priv(dev);
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struct display_timing timings;
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phys_addr_t fb_base, fb_size;
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const char *format;
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u32 value;
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int err;
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if (!ofnode_valid(framebuffer))
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return -EINVAL;
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err = clk_get_by_name(dev, "pxlclk", &priv->pxlclk);
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if (err) {
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dev_err(dev, "failed to get pixel clock\n");
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return err;
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}
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err = clk_get_by_name(dev, "aclk", &priv->aclk);
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if (err) {
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dev_err(dev, "failed to get AXI clock\n");
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goto fail_aclk;
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}
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err = ofnode_decode_display_timing(dev_ofnode(dev), 1, &timings);
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if (err) {
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dev_err(dev, "failed to get any display timings\n");
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goto fail_timings;
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}
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err = malidp_update_timings_from_edid(dev, &timings);
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if (err) {
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printf("malidp_update_timings_from_edid failed: %d\n", err);
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goto fail_timings;
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}
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fb_base = ofnode_get_addr_size(framebuffer, "reg", &fb_size);
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if (fb_base != FDT_ADDR_T_NONE) {
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uc_plat->base = fb_base;
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uc_plat->size = fb_size;
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} else {
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printf("cannot get address size for framebuffer\n");
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}
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err = ofnode_read_u32(framebuffer, "width", &value);
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if (err)
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goto fail_timings;
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uc_priv->xsize = (ushort)value;
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err = ofnode_read_u32(framebuffer, "height", &value);
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if (err)
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goto fail_timings;
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uc_priv->ysize = (ushort)value;
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format = ofnode_read_string(framebuffer, "format");
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if (!format) {
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err = -EINVAL;
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goto fail_timings;
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} else if (!strncmp(format, "a8r8g8b8", 8)) {
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uc_priv->bpix = VIDEO_BPP32;
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}
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uc_priv->rot = 0;
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priv->base_addr = (phys_addr_t)dev_read_addr(dev);
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clk_enable(&priv->pxlclk);
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clk_enable(&priv->aclk);
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value = malidp_get_hwid(priv->base_addr);
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printf("Display: Arm Mali DP%3x r%dp%d\n", MALIDP_PRODUCT_ID(value),
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(value >> 12) & 0xf, (value >> 8) & 0xf);
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if (MALIDP_PRODUCT_ID(value) == MALIDP500) {
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/* DP500 is special */
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priv->modeset_regs_offset = 0x28;
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priv->dc_status_addr = priv->base_addr;
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priv->dc_control_addr = priv->base_addr + 0xc;
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priv->cval_addr = priv->base_addr + 0xf00;
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priv->config_bit_shift = 17;
|
|
|
|
priv->clear_irq = 0;
|
|
|
|
} else {
|
|
|
|
priv->modeset_regs_offset = 0x30;
|
|
|
|
priv->dc_status_addr = priv->base_addr + MALIDP_DC_STATUS;
|
|
|
|
priv->dc_control_addr = priv->base_addr + MALIDP_DC_CONTROL;
|
|
|
|
priv->cval_addr = priv->base_addr + MALIDP_DC_CFG_VALID;
|
|
|
|
priv->config_bit_shift = 16;
|
|
|
|
priv->clear_irq = MALIDP_REG_CLEARIRQ;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* enter config mode */
|
|
|
|
err = malidp_enter_config(priv);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
/* disable interrupts */
|
|
|
|
writel(0, priv->dc_status_addr + MALIDP_REG_MASKIRQ);
|
|
|
|
writel(0xffffffff, priv->dc_status_addr + priv->clear_irq);
|
|
|
|
|
|
|
|
err = malidp_setup_mode(priv, &timings);
|
|
|
|
if (err)
|
|
|
|
goto fail_timings;
|
|
|
|
|
|
|
|
malidp_setup_layer(priv, &timings, MALIDP_LAYER_LV1,
|
|
|
|
(phys_addr_t)uc_plat->base);
|
|
|
|
|
|
|
|
err = malidp_leave_config(priv);
|
|
|
|
if (err)
|
|
|
|
goto fail_timings;
|
|
|
|
|
|
|
|
malidp_set_configvalid(priv);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
fail_timings:
|
|
|
|
clk_free(&priv->aclk);
|
|
|
|
fail_aclk:
|
|
|
|
clk_free(&priv->pxlclk);
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int malidp_bind(struct udevice *dev)
|
|
|
|
{
|
|
|
|
struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
|
|
|
|
|
|
|
|
/* choose max possible size: 2K x 2K, XRGB888 framebuffer */
|
|
|
|
uc_plat->size = 4 * 2048 * 2048;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct udevice_id malidp_ids[] = {
|
|
|
|
{ .compatible = "arm,mali-dp500" },
|
|
|
|
{ .compatible = "arm,mali-dp550" },
|
|
|
|
{ .compatible = "arm,mali-dp650" },
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
U_BOOT_DRIVER(mali_dp) = {
|
|
|
|
.name = "mali_dp",
|
|
|
|
.id = UCLASS_VIDEO,
|
|
|
|
.of_match = malidp_ids,
|
|
|
|
.bind = malidp_bind,
|
|
|
|
.probe = malidp_probe,
|
|
|
|
.priv_auto_alloc_size = sizeof(struct malidp_priv),
|
|
|
|
.ops = &malidp_ops,
|
|
|
|
};
|