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19 lines
480 B
C
19 lines
480 B
C
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2022, Humberto Naves <hsnaves@gmail.com>
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*
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* Adapted from socfpga_de0_nano_soc.h
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*/
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#ifndef __CONFIG_TERASIC_DE10_STANDARD_H__
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#define __CONFIG_TERASIC_DE10_STANDARD_H__
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#include <asm/arch/base_addr_ac5.h>
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/* Memory configurations */
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#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */
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/* The rest of the configuration is shared */
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#include <configs/socfpga_common.h>
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#endif /* __CONFIG_TERASIC_DE10_STANDARD_H__ */
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