2012-05-15 22:15:51 +00:00
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/*
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* Copyright (C) 2012 Renesas Electronics Europe Ltd.
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* Copyright (C) 2012 Phil Edworthy
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* Copyright (C) 2008 Renesas Solutions Corp.
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* Copyright (C) 2008 Nobuhiro Iwamatsu
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*
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* Based on board/renesas/rsk7264/lowlevel_init.S
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*
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2013-07-08 07:37:19 +00:00
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* SPDX-License-Identifier: GPL-2.0+
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2012-05-15 22:15:51 +00:00
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/processor.h>
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#include <asm/macro.h>
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.global lowlevel_init
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.text
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.align 2
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lowlevel_init:
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/* Flush and enable caches (data cache in write-through mode) */
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write32 CCR1_A ,CCR1_D
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/* Disable WDT */
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write16 WTCSR_A, WTCSR_D
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write16 WTCNT_A, WTCNT_D
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/* Disable Register Bank interrupts */
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write16 IBNR_A, IBNR_D
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/* Set clocks based on 13.225MHz xtal */
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write16 FRQCR_A, FRQCR_D /* CPU=266MHz, I=133MHz, P=66MHz */
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/* Enable all peripherals */
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write8 STBCR3_A, STBCR3_D
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write8 STBCR4_A, STBCR4_D
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write8 STBCR5_A, STBCR5_D
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write8 STBCR6_A, STBCR6_D
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write8 STBCR7_A, STBCR7_D
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write8 STBCR8_A, STBCR8_D
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write8 STBCR9_A, STBCR9_D
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write8 STBCR10_A, STBCR10_D
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/* SCIF7 and IIC2 */
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write16 PJCR3_A, PJCR3_D /* TXD7 */
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write16 PECR1_A, PECR1_D /* RXD7, SDA2, SCL2 */
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/* Configure bus (CS0) */
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write16 PFCR3_A, PFCR3_D /* A24 */
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write16 PFCR2_A, PFCR2_D /* A23 and CS1# */
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write16 PBCR5_A, PBCR5_D /* A22, A21, A20 */
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write16 PCCR0_A, PCCR0_D /* DQMLL#, RD/WR# */
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write32 CS0WCR_A, CS0WCR_D
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write32 CS0BCR_A, CS0BCR_D
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/* Configure SDRAM (CS3) */
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write16 PCCR2_A, PCCR2_D /* CS3# */
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write16 PCCR1_A, PCCR1_D /* CKE, CAS#, RAS#, DQMLU# */
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write16 PCCR0_A, PCCR0_D /* DQMLL#, RD/WR# */
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write32 CS3BCR_A, CS3BCR_D
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write32 CS3WCR_A, CS3WCR_D
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write32 SDCR_A, SDCR_D
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write32 RTCOR_A, RTCOR_D
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write32 RTCSR_A, RTCSR_D
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/* Configure ethernet (CS1) */
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write16 PHCR1_A, PHCR1_D /* PINT5 on PH5 */
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write16 PHCR0_A, PHCR0_D
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write16 PFCR2_A, PFCR2_D /* CS1# */
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write32 CS1BCR_A, CS1BCR_D /* Big endian */
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write32 CS1WCR_A, CS1WCR_D /* 1 cycle */
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write16 PJDR1_A, PJDR1_D /* FIFO-SEL = 1 */
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write16 PJIOR1_A, PJIOR1_D
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/* wait 200us */
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mov.l REPEAT_D, r3
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mov #0, r2
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repeat0:
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add #1, r2
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cmp/hs r3, r2
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bf repeat0
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nop
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mov.l SDRAM_MODE, r1
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mov #0, r0
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mov.l r0, @r1
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nop
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rts
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.align 4
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CCR1_A: .long CCR1
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CCR1_D: .long 0x0000090B
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STBCR3_A: .long 0xFFFE0408
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STBCR4_A: .long 0xFFFE040C
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STBCR5_A: .long 0xFFFE0410
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STBCR6_A: .long 0xFFFE0414
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STBCR7_A: .long 0xFFFE0418
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STBCR8_A: .long 0xFFFE041C
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STBCR9_A: .long 0xFFFE0440
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STBCR10_A: .long 0xFFFE0444
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STBCR3_D: .long 0x0000001A
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STBCR4_D: .long 0x00000000
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STBCR5_D: .long 0x00000000
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STBCR6_D: .long 0x00000000
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STBCR7_D: .long 0x00000012
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STBCR8_D: .long 0x00000009
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STBCR9_D: .long 0x00000000
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STBCR10_D: .long 0x00000010
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WTCSR_A: .long 0xFFFE0000
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WTCNT_A: .long 0xFFFE0002
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WTCSR_D: .word 0xA518
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WTCNT_D: .word 0x5A00
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IBNR_A: .long 0xFFFE080E
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IBNR_D: .word 0x0000
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.align 2
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FRQCR_A: .long 0xFFFE0010
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FRQCR_D: .word 0x0015
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.align 2
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PJCR3_A: .long 0xFFFE3908
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PJCR3_D: .word 0x5000
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.align 2
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PECR1_A: .long 0xFFFE388C
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PECR1_D: .word 0x2011
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.align 2
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PFCR3_A: .long 0xFFFE38A8
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PFCR2_A: .long 0xFFFE38AA
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PBCR5_A: .long 0xFFFE3824
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PFCR3_D: .word 0x0010
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PFCR2_D: .word 0x0101
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PBCR5_D: .word 0x0111
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.align 2
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CS0WCR_A: .long 0xFFFC0028
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CS0WCR_D: .long 0x00000341
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CS0BCR_A: .long 0xFFFC0004
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CS0BCR_D: .long 0x00000400
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PCCR2_A: .long 0xFFFE384A
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PCCR1_A: .long 0xFFFE384C
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PCCR0_A: .long 0xFFFE384E
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PCCR2_D: .word 0x0001
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PCCR1_D: .word 0x1111
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PCCR0_D: .word 0x1111
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.align 2
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CS3BCR_A: .long 0xFFFC0010
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CS3BCR_D: .long 0x00004400
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CS3WCR_A: .long 0xFFFC0034
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CS3WCR_D: .long 0x00004912
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SDCR_A: .long 0xFFFC004C
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SDCR_D: .long 0x00000811
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RTCOR_A: .long 0xFFFC0058
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RTCOR_D: .long 0xA55A0035
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RTCSR_A: .long 0xFFFC0050
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RTCSR_D: .long 0xA55A0010
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.align 2
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SDRAM_MODE: .long 0xFFFC5460
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REPEAT_D: .long 0x000033F1
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PHCR1_A: .long 0xFFFE38EC
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PHCR0_A: .long 0xFFFE38EE
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PHCR1_D: .word 0x2222
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PHCR0_D: .word 0x2222
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.align 2
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CS1BCR_A: .long 0xFFFC0008
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CS1BCR_D: .long 0x00000400
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CS1WCR_A: .long 0xFFFC002C
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CS1WCR_D: .long 0x00000080
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PJDR1_A: .long 0xFFFE3914
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PJDR1_D: .word 0x0000
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.align 2
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PJIOR1_A: .long 0xFFFE3910
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PJIOR1_D: .word 0x8000
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.align 2
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