u-boot/arch/arm/dts/fsl-sch-30842.dtsi

// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
 * Device tree fragment for RCW SCH-30842 card
 *
 * Copyright 2019-2021 NXP
 */

/*
 * SCH-30842 is a single port add-on card used with various FSL QDS boards.
 * It integrates a AQR112 PHY, which supports several protocols - SGMII,
 * SGMII-2500, USXGMII, 10GBase-R.
 * PHY address is 0x02.
 */
phy@02 {
	reg = <0x02>;
	mdi-reversal = <1>;
	smb-addr = <0x25>;
};
arm: dts: ls1028a: define QDS networking protocol combinations Includes DT definition for the following serdes protocols using various PHY cards: 85xx, 13xx, 65xx, 9999, 7777. Note that the default device tree for QDS now uses 85xx. Enabling any of the others requires patching the fsl-ls1028a-qds.dtsi file (the includes at the bottom of the file). The phy-handle is specified as a path rather than a label because it is possible to use the #include multiple times (meaning that more than one PHY riser card of one type is inserted), and therefore, there would be duplicate labels with the same name. LBRW means that the board needs lane B rework before using this dtsi. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> 2021-01-27 11:00:00 +00:00			`// SPDX-License-Identifier: GPL-2.0+ OR X11`
			`/*`
			`* Device tree fragment for RCW SCH-30842 card`
			`*`
net: update NXP copyright text NXP Legal insists that the following are not fine: - Saying "NXP Semiconductors" instead of "NXP", since the company's registered name is "NXP" - Putting a "(c)" sign in the copyright string - Putting a comma in the copyright string The only accepted copyright string format is "Copyright <year-range> NXP". This patch changes the copyright headers in the networking files that were sent by me, or derived from code sent by me. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> 2021-09-17 11:27:13 +00:00			`* Copyright 2019-2021 NXP`
arm: dts: ls1028a: define QDS networking protocol combinations Includes DT definition for the following serdes protocols using various PHY cards: 85xx, 13xx, 65xx, 9999, 7777. Note that the default device tree for QDS now uses 85xx. Enabling any of the others requires patching the fsl-ls1028a-qds.dtsi file (the includes at the bottom of the file). The phy-handle is specified as a path rather than a label because it is possible to use the #include multiple times (meaning that more than one PHY riser card of one type is inserted), and therefore, there would be duplicate labels with the same name. LBRW means that the board needs lane B rework before using this dtsi. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> 2021-01-27 11:00:00 +00:00			`*/`

			`/*`
			`* SCH-30842 is a single port add-on card used with various FSL QDS boards.`
			`* It integrates a AQR112 PHY, which supports several protocols - SGMII,`
net: replace the "xfi" phy-mode with "10gbase-r" As part of the effort of making U-Boot work with the same device tree as Linux, there is an issue with the "xfi" phy-mode. To be precise, in Linux there was a discussion (for those who have time to read: https://lore.kernel.org/netdev/1576768881-24971-2-git-send-email-madalin.bucur@oss.nxp.com/) which led to a patch: https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit/?id=c114574ebfdf42f826776f717c8056a00fa94881 TL;DR: "xfi" was standardized in Linux as "10gbase-r". This patch changes the relevant occurrences in U-Boot to use "10gbase-r" instead of "xfi" wherever applicable. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> 2021-09-18 12:32:34 +00:00			`* SGMII-2500, USXGMII, 10GBase-R.`
arm: dts: ls1028a: define QDS networking protocol combinations Includes DT definition for the following serdes protocols using various PHY cards: 85xx, 13xx, 65xx, 9999, 7777. Note that the default device tree for QDS now uses 85xx. Enabling any of the others requires patching the fsl-ls1028a-qds.dtsi file (the includes at the bottom of the file). The phy-handle is specified as a path rather than a label because it is possible to use the #include multiple times (meaning that more than one PHY riser card of one type is inserted), and therefore, there would be duplicate labels with the same name. LBRW means that the board needs lane B rework before using this dtsi. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> 2021-01-27 11:00:00 +00:00			`* PHY address is 0x02.`
			`*/`
			`phy@02 {`
			`reg = <0x02>;`
			`mdi-reversal = <1>;`
			`smb-addr = <0x25>;`
			`};`