2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2012-01-11 01:45:01 +00:00
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/*
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* (C) Copyright 2008, 2011 Renesas Solutions Corp.
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*
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* SH7734 Internal I/O register
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*/
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#ifndef _ASM_CPU_SH7734_H_
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#define _ASM_CPU_SH7734_H_
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#define CCR 0xFF00001C
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#define CACHE_OC_NUM_WAYS 4
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#define CCR_CACHE_INIT 0x0000090d
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/* SCIF */
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#define SCIF0_BASE 0xFFE40000
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#define SCIF1_BASE 0xFFE41000
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#define SCIF2_BASE 0xFFE42000
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#define SCIF3_BASE 0xFFE43000
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#define SCIF4_BASE 0xFFE44000
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#define SCIF5_BASE 0xFFE45000
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/* Timer */
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2012-08-21 04:14:46 +00:00
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#define TMU_BASE 0xFFD80000
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2012-01-11 01:45:01 +00:00
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2012-05-09 07:00:01 +00:00
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/* PFC */
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#define PMMR (0xFFFC0000)
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#define MODESEL0 (0xFFFC004C)
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#define MODESEL2 (MODESEL0 + 0x4)
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#define MODESEL2_INIT (0x00003000)
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#define IPSR0 (0xFFFC001C)
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#define IPSR1 (IPSR0 + 0x4)
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#define IPSR2 (IPSR0 + 0x8)
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#define IPSR3 (IPSR0 + 0xC)
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#define IPSR4 (IPSR0 + 0x10)
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#define IPSR5 (IPSR0 + 0x14)
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#define IPSR6 (IPSR0 + 0x18)
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#define IPSR7 (IPSR0 + 0x1C)
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#define IPSR8 (IPSR0 + 0x20)
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#define IPSR9 (IPSR0 + 0x24)
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#define IPSR10 (IPSR0 + 0x28)
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#define IPSR11 (IPSR0 + 0x2C)
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#define GPSR0 (0xFFFC0004)
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#define GPSR1 (GPSR0 + 0x4)
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#define GPSR2 (GPSR0 + 0x8)
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#define GPSR3 (GPSR0 + 0xC)
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#define GPSR4 (GPSR0 + 0x10)
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#define GPSR5 (GPSR0 + 0x14)
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2012-01-11 01:45:01 +00:00
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#endif /* _ASM_CPU_SH7734_H_ */
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