mirror of
https://github.com/AsahiLinux/u-boot
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71 lines
1.6 KiB
C
71 lines
1.6 KiB
C
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/*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
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*
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* Modified from coreboot src/soc/intel/baytrail/include/soc/iomap.h
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _BAYTRAIL_IOMAP_H_
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#define _BAYTRAIL_IOMAP_H_
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/* Memory Mapped IO bases */
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/* PCI Configuration Space */
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#define MCFG_BASE_ADDRESS CONFIG_PCIE_ECAM_BASE
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#define MCFG_BASE_SIZE 0x10000000
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/* Temporary Base Address */
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#define TEMP_BASE_ADDRESS 0xfd000000
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/* Transactions in this range will abort */
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#define ABORT_BASE_ADDRESS 0xfeb00000
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#define ABORT_BASE_SIZE 0x00100000
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/* High Performance Event Timer */
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#define HPET_BASE_ADDRESS 0xfed00000
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#define HPET_BASE_SIZE 0x400
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/* SPI Bus */
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#define SPI_BASE_ADDRESS 0xfed01000
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#define SPI_BASE_SIZE 0x400
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/* Power Management Controller */
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#define PMC_BASE_ADDRESS 0xfed03000
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#define PMC_BASE_SIZE 0x400
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/* Power Management Unit */
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#define PUNIT_BASE_ADDRESS 0xfed05000
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#define PUNIT_BASE_SIZE 0x800
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/* Intel Legacy Block */
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#define ILB_BASE_ADDRESS 0xfed08000
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#define ILB_BASE_SIZE 0x400
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/* IO Memory */
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#define IO_BASE_ADDRESS 0xfed0c000
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#define IO_BASE_OFFSET_GPSCORE 0x0000
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#define IO_BASE_OFFSET_GPNCORE 0x1000
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#define IO_BASE_OFFSET_GPSSUS 0x2000
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#define IO_BASE_SIZE 0x4000
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/* Root Complex Base Address */
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#define RCBA_BASE_ADDRESS 0xfed1c000
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#define RCBA_BASE_SIZE 0x400
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/* MODPHY */
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#define MPHY_BASE_ADDRESS 0xfef00000
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#define MPHY_BASE_SIZE 0x100000
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/* IO Port bases */
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#define ACPI_BASE_ADDRESS 0x0400
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#define ACPI_BASE_SIZE 0x80
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#define GPIO_BASE_ADDRESS 0x0500
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#define GPIO_BASE_SIZE 0x100
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#define SMBUS_BASE_ADDRESS 0xefa0
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#endif /* _BAYTRAIL_IOMAP_H_ */
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