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u-boot/arch/arm/dts/rk3326-odroid-go2.dts

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rockchip: px30: sync Odroid Go Advance devicetree from Linux Get the devicetree from mainline Linux and include it for U-Boot uses. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-01 09:28:41 +00:00
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 Hardkernel Co., Ltd
* Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "rk3326.dtsi"
/ {
model = "ODROID-GO Advance";
compatible = "hardkernel,rk3326-odroid-go2", "rockchip,rk3326";
chosen {
stdout-path = "serial2:115200n8";
};
backlight: backlight {
compatible = "pwm-backlight";
power-supply = <&vcc_bl>;
pwms = <&pwm1 0 25000 0>;
};
adc-joystick {
compatible = "adc-joystick";
io-channels = <&saradc 1>,
<&saradc 2>;
#address-cells = <1>;
#size-cells = <0>;
axis@0 {
reg = <0>;
abs-range = <172 772>;
abs-fuzz = <10>;
abs-flat = <10>;
linux,code = <ABS_X>;
};
axis@1 {
reg = <1>;
abs-range = <278 815>;
abs-fuzz = <10>;
abs-flat = <10>;
linux,code = <ABS_Y>;
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&btn_pins>;
/*
* *** ODROIDGO2-Advance Switch layout ***
* |------------------------------------------------|
* | sw15 sw16 |
* |------------------------------------------------|
* | sw1 |-------------------| sw8 |
* | sw3 sw4 | | sw7 sw5 |
* | sw2 | LCD Display | sw6 |
* | | | |
* | |-------------------| |
* | sw9 sw10 sw11 sw12 sw13 sw14 |
* |------------------------------------------------|
*/
sw1 {
gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_LOW>;
label = "DPAD-UP";
linux,code = <BTN_DPAD_UP>;
};
sw2 {
gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_LOW>;
label = "DPAD-DOWN";
linux,code = <BTN_DPAD_DOWN>;
};
sw3 {
gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>;
label = "DPAD-LEFT";
linux,code = <BTN_DPAD_LEFT>;
};
sw4 {
gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_LOW>;
label = "DPAD-RIGHT";
linux,code = <BTN_DPAD_RIGHT>;
};
sw5 {
gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_LOW>;
label = "BTN-A";
linux,code = <BTN_EAST>;
};
sw6 {
gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>;
label = "BTN-B";
linux,code = <BTN_SOUTH>;
};
sw7 {
gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>;
label = "BTN-Y";
linux,code = <BTN_WEST>;
};
sw8 {
gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>;
label = "BTN-X";
linux,code = <BTN_NORTH>;
};
sw9 {
gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_LOW>;
label = "F1";
linux,code = <BTN_TRIGGER_HAPPY1>;
};
sw10 {
gpios = <&gpio2 RK_PA1 GPIO_ACTIVE_LOW>;
label = "F2";
linux,code = <BTN_TRIGGER_HAPPY2>;
};
sw11 {
gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
label = "F3";
linux,code = <BTN_TRIGGER_HAPPY3>;
};
sw12 {
gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_LOW>;
label = "F4";
linux,code = <BTN_TRIGGER_HAPPY4>;
};
sw13 {
gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_LOW>;
label = "F5";
linux,code = <BTN_TRIGGER_HAPPY5>;
};
sw14 {
gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_LOW>;
label = "F6";
linux,code = <BTN_TRIGGER_HAPPY6>;
};
sw15 {
gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>;
label = "TOP-LEFT";
linux,code = <BTN_TL>;
};
sw16 {
gpios = <&gpio2 RK_PA7 GPIO_ACTIVE_LOW>;
label = "TOP-RIGHT";
linux,code = <BTN_TR>;
};
};
leds: gpio-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&blue_led_pin>;
blue_led: led-0 {
label = "blue:heartbeat";
gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
rk817-sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,name = "rockchip,rk817-codec";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,widgets =
"Microphone", "Mic Jack",
"Headphone", "Headphone Jack";
simple-audio-card,routing =
"MIC_IN", "Mic Jack",
"Headphone Jack", "HPOL",
"Headphone Jack", "HPOR";
simple-audio-card,hp-det-gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>;
simple-audio-card,codec-hp-det = <1>;
simple-audio-card,cpu {
sound-dai = <&i2s1_2ch>;
};
simple-audio-card,codec {
sound-dai = <&rk817_codec>;
};
};
vccsys: vccsys {
compatible = "regulator-fixed";
regulator-name = "vcc3v8_sys";
regulator-always-on;
regulator-min-microvolt = <3800000>;
regulator-max-microvolt = <3800000>;
};
vcc_host: vcc_host {
compatible = "regulator-fixed";
regulator-name = "vcc_host";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
vin-supply = <&vccsys>;
};
};
&cpu0 {
cpu-supply = <&vdd_arm>;
};
&cpu1 {
cpu-supply = <&vdd_arm>;
};
&cpu2 {
cpu-supply = <&vdd_arm>;
};
&cpu3 {
cpu-supply = <&vdd_arm>;
};
&cru {
assigned-clocks = <&cru PLL_NPLL>,
<&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
<&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
<&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>,
<&cru PLL_CPLL>;
assigned-clock-rates = <1188000000>,
<200000000>, <200000000>,
<150000000>, <150000000>,
<100000000>, <200000000>,
<17000000>;
};
&display_subsystem {
status = "okay";
};
&dsi {
status = "okay";
ports {
mipi_out: port@1 {
reg = <1>;
mipi_out_panel: endpoint {
remote-endpoint = <&mipi_in_panel>;
};
};
};
panel@0 {
compatible = "elida,kd35t133";
reg = <0>;
backlight = <&backlight>;
iovcc-supply = <&vcc_lcd>;
reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
vdd-supply = <&vcc_lcd>;
port {
mipi_in_panel: endpoint {
remote-endpoint = <&mipi_out_panel>;
};
};
};
};
&dsi_dphy {
status = "okay";
};
&gpu {
mali-supply = <&vdd_logic>;
status = "okay";
};
&i2c0 {
clock-frequency = <400000>;
i2c-scl-falling-time-ns = <16>;
i2c-scl-rising-time-ns = <280>;
status = "okay";
rk817: pmic@20 {
compatible = "rockchip,rk817";
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default", "pmic-sleep",
"pmic-power-off", "pmic-reset";
pinctrl-0 = <&pmic_int>;
pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;
clock-output-names = "rk808-clkout1", "xin32k";
vcc1-supply = <&vccsys>;
vcc2-supply = <&vccsys>;
vcc3-supply = <&vccsys>;
vcc4-supply = <&vccsys>;
vcc5-supply = <&vccsys>;
vcc6-supply = <&vccsys>;
vcc7-supply = <&vccsys>;
pinctrl_rk8xx: pinctrl_rk8xx {
gpio-controller;
#gpio-cells = <2>;
rk817_ts_gpio1: rk817_ts_gpio1 {
pins = "gpio_ts";
function = "pin_fun1";
/* output-low; */
/* input-enable; */
};
rk817_gt_gpio2: rk817_gt_gpio2 {
pins = "gpio_gt";
function = "pin_fun1";
};
rk817_pin_ts: rk817_pin_ts {
pins = "gpio_ts";
function = "pin_fun0";
};
rk817_pin_gt: rk817_pin_gt {
pins = "gpio_gt";
function = "pin_fun0";
};
rk817_slppin_null: rk817_slppin_null {
pins = "gpio_slp";
function = "pin_fun0";
};
rk817_slppin_slp: rk817_slppin_slp {
pins = "gpio_slp";
function = "pin_fun1";
};
rk817_slppin_pwrdn: rk817_slppin_pwrdn {
pins = "gpio_slp";
function = "pin_fun2";
};
rk817_slppin_rst: rk817_slppin_rst {
pins = "gpio_slp";
function = "pin_fun3";
};
};
regulators {
vdd_logic: DCDC_REG1 {
regulator-name = "vdd_logic";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1150000>;
regulator-ramp-delay = <6001>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <950000>;
};
};
vdd_arm: DCDC_REG2 {
regulator-name = "vdd_arm";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <950000>;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_3v3: DCDC_REG4 {
regulator-name = "vcc_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_1v8: LDO_REG2 {
regulator-name = "vcc_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd_1v0: LDO_REG3 {
regulator-name = "vdd_1v0";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vcc3v3_pmu: LDO_REG4 {
regulator-name = "vcc3v3_pmu";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vccio_sd: LDO_REG5 {
regulator-name = "vccio_sd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_sd: LDO_REG6 {
regulator-name = "vcc_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_bl: LDO_REG7 {
regulator-name = "vcc_bl";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_lcd: LDO_REG8 {
regulator-name = "vcc_lcd";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <2800000>;
};
};
vcc_cam: LDO_REG9 {
regulator-name = "vcc_cam";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
};
battery {
compatible = "rk817,battery";
ocv_table = <3500 3625 3685 3697 3718 3735 3748
3760 3774 3788 3802 3816 3834 3853
3877 3908 3946 3975 4018 4071 4106>;
/* KPL605475 Battery Spec */
/*
Capacity : 3.7V 3000mA
Normal Voltage = 3.7V
Cut-Off Voltage : 3.1V
Internal Impedance : 180 mOhm
Charging Voltage : 4.2V
Charging Voltage Max : 4.25V
Sample resister : 10 mohm
*/
design_capacity = <3000>;
design_qmax = <3000>;
bat_res = <180>;
sleep_enter_current = <300>;
sleep_exit_current = <300>;
sleep_filter_current = <100>;
power_off_thresd = <3500>;
zero_algorithm_vol = <3700>;
max_soc_offset = <60>;
monitor_sec = <5>;
virtual_power = <0>;
sample_res = <10>;
};
charger {
compatible = "rk817,charger";
min_input_voltage = <4500>;
max_input_current = <1500>;
max_chrg_current = <2000>;
max_chrg_voltage = <4200>;
chrg_term_mode = <0>;
chrg_finish_cur = <300>;
virtual_power = <0>;
sample_res = <10>;
/* P.C.B rev0.2 DC Detect & Charger Status LED GPIO */
dc_det_gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
chg_led_gpio = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
extcon = <&u2phy>;
};
rk817_codec: codec {
#sound-dai-cells = <0>;
compatible = "rockchip,rk817-codec";
clocks = <&cru SCLK_I2S1_OUT>;
clock-names = "mclk";
pinctrl-names = "default";
pinctrl-0 = <&i2s1_2ch_mclk>;
hp-volume = <20>;
spk-volume = <3>;
status = "okay";
};
};
};
/* EXT Header(P2): 7(SCL:GPIO0.C2), 8(SDA:GPIO0.C3) */
&i2c1 {
clock-frequency = <400000>;
status = "okay";
};
/* I2S 1 Channel Used */
&i2s1_2ch {
status = "okay";
};
&io_domains {
vccio1-supply = <&vcc_3v3>;
vccio2-supply = <&vccio_sd>;
vccio3-supply = <&vcc_3v3>;
vccio4-supply = <&vcc_3v3>;
vccio5-supply = <&vcc_3v3>;
vccio6-supply = <&vcc_3v3>;
status = "okay";
};
&pmu_io_domains {
pmuio1-supply = <&vcc3v3_pmu>;
pmuio2-supply = <&vcc3v3_pmu>;
status = "okay";
};
&pwm1 {
status = "okay";
};
&saradc {
vref-supply = <&vcc_1v8>;
status = "okay";
};
&sdmmc {
bus-width = <4>;
cap-sd-highspeed;
card-detect-delay = <200>;
cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>; /*[> CD GPIO <]*/
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
vmmc-supply = <&vcc_sd>;
vqmmc-supply = <&vccio_sd>;
status = "okay";
};
rockchip: px30: add support for SFC for Odroid Go Advance The Odroid Go Advance uses a Rockchip Serial Flash Controller with an XT25F128B SPI NOR flash chip. This adds support for both. Note that while both the controller and chip support quad mode, only two lines are connected to the chip. Changing the pinctrl to bus2 and setting tx and rx lines to 2 for this reason. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-08-05 08:27:52 +00:00
&sfc {
rockchip: px30: sync serial flash controller bindings with mainline The devicetree submitted and approved for the mainline linux kernel is slightly different than the one present here. This syncs both devicetrees (for the Rockchip SFC node at least) present on the PX30 and the Odroid Go Advance. Changes include renaming the flash node, reordering the values in the SFC node for the rk3326-odroid-go2, changing the name of the cs pinctrl node to cs0, and updating the u-boot specific tree to utilize the new flash node value. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-08-21 01:46:58 +00:00
pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus2>;
pinctrl-names = "default";
rockchip: px30: add support for SFC for Odroid Go Advance The Odroid Go Advance uses a Rockchip Serial Flash Controller with an XT25F128B SPI NOR flash chip. This adds support for both. Note that while both the controller and chip support quad mode, only two lines are connected to the chip. Changing the pinctrl to bus2 and setting tx and rx lines to 2 for this reason. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-08-05 08:27:52 +00:00
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
rockchip: px30: sync serial flash controller bindings with mainline The devicetree submitted and approved for the mainline linux kernel is slightly different than the one present here. This syncs both devicetrees (for the Rockchip SFC node at least) present on the PX30 and the Odroid Go Advance. Changes include renaming the flash node, reordering the values in the SFC node for the rk3326-odroid-go2, changing the name of the cs pinctrl node to cs0, and updating the u-boot specific tree to utilize the new flash node value. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-08-21 01:46:58 +00:00
flash@0 {
rockchip: px30: add support for SFC for Odroid Go Advance The Odroid Go Advance uses a Rockchip Serial Flash Controller with an XT25F128B SPI NOR flash chip. This adds support for both. Note that while both the controller and chip support quad mode, only two lines are connected to the chip. Changing the pinctrl to bus2 and setting tx and rx lines to 2 for this reason. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-08-05 08:27:52 +00:00
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <108000000>;
spi-rx-bus-width = <2>;
rockchip: px30: sync serial flash controller bindings with mainline The devicetree submitted and approved for the mainline linux kernel is slightly different than the one present here. This syncs both devicetrees (for the Rockchip SFC node at least) present on the PX30 and the Odroid Go Advance. Changes include renaming the flash node, reordering the values in the SFC node for the rk3326-odroid-go2, changing the name of the cs pinctrl node to cs0, and updating the u-boot specific tree to utilize the new flash node value. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-08-21 01:46:58 +00:00
spi-tx-bus-width = <1>;
rockchip: px30: add support for SFC for Odroid Go Advance The Odroid Go Advance uses a Rockchip Serial Flash Controller with an XT25F128B SPI NOR flash chip. This adds support for both. Note that while both the controller and chip support quad mode, only two lines are connected to the chip. Changing the pinctrl to bus2 and setting tx and rx lines to 2 for this reason. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-08-05 08:27:52 +00:00
};
};
rockchip: px30: sync Odroid Go Advance devicetree from Linux Get the devicetree from mainline Linux and include it for U-Boot uses. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-01 09:28:41 +00:00
&tsadc {
status = "okay";
};
&u2phy {
status = "okay";
u2phy_host: host-port {
status = "okay";
};
u2phy_otg: otg-port {
status = "disabled";
};
};
&usb20_otg {
status = "okay";
};
/* EXT Header(P2): 2(RXD:GPIO1.C0),3(TXD:.C1),4(CTS:.C2),5(RTS:.C3) */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_xfer &uart1_cts>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2m1_xfer>;
status = "okay";
};
&vopb {
status = "okay";
};
&vopb_mmu {
status = "okay";
};
&pinctrl {
btns {
btn_pins: btn-pins {
rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
<1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>,
<1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
<1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>,
<1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>,
<1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>,
<1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>,
<1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>,
<2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>,
<2 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>,
<2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
<2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>,
<2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>,
<2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>,
<2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
<2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
headphone {
hp_det: hp-det {
rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
leds {
blue_led_pin: blue-led-pin {
rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
dc_det: dc-det {
rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
};
pmic_int: pmic-int {
rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
};
soc_slppin_gpio: soc_slppin_gpio {
rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>;
};
soc_slppin_rst: soc_slppin_rst {
rockchip,pins = <0 RK_PA4 2 &pcfg_pull_none>;
};
soc_slppin_slp: soc_slppin_slp {
rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>;
};
};
};
Reference in a new issue Copy permalink