Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-12-11 22:03:15 +00:00
Code Issues Projects Releases Packages Wiki Activity
u-boot/arch/arm/mach-rockchip/save_boot_param.S

70 lines
1.3 KiB
ArmAsm
Raw Normal View History

rockchip: rk3036: Add core Soc start-up code rk3036 only 4K size SRAM for SPL, so only support timer, uart, sdram driver in SPL stage, when finish initial sdram, back to bootrom.And in rk3036 sdmmc and debug uart use same iomux, so if you want to boot from sdmmc, you must disable debug uart. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed build error for chromebook_jerry, firefly-rk3288: Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - Fix build error for chromebook_jerry, firefly-rk3288
2015-11-17 06:20:27 +00:00
/*
rockchip: add option to change method of loading u-boot If we would like to boot from SD card, we have to implement mmc driver in SPL stage, and get a slightly large SPL binary. Rockchip SoC's bootrom code has the ability to load spl and u-boot, then boot. If CONFIG_ROCKCHIP_SPL_BACK_TO_BROM is enabled, the spl will return to bootrom in board_init_f(), then bootrom loads u-boot binary. Loading sequence after rework: bootrom ==> spl ==> bootrom ==> u-boot Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed up spelling of U-Boot, boorom, opinion->option, Rochchip: Signed-off-by: Simon Glass <sjg@chromium.org>
2016-07-12 11:09:49 +00:00
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
rockchip: back-to-bootrom: add 'back-to-bootrom' support for AArch64 The back-to-bootrom support for Rockchip is equivalent to an (assembly) implementation of setjmp/longjmp (i.e. it saves the stack-pointer, link-register and callee-saved registers). Up until now, this had only been implemented for AArch32 (i.e. ARMv7 or older), which puts the new ARMv8 devices (which boot in AArch64 mode) at a slight disadvantage. To allow use of the 'back-to-bootrom' feature on new devices (e.g. the RK3368), this commit adds an implementation for AArch64. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-06-22 22:05:38 +00:00
* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
rockchip: rk3036: Add core Soc start-up code rk3036 only 4K size SRAM for SPL, so only support timer, uart, sdram driver in SPL stage, when finish initial sdram, back to bootrom.And in rk3036 sdmmc and debug uart use same iomux, so if you want to boot from sdmmc, you must disable debug uart. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed build error for chromebook_jerry, firefly-rk3288: Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - Fix build error for chromebook_jerry, firefly-rk3288
2015-11-17 06:20:27 +00:00
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/linkage.h>
rockchip: back-to-bootrom: add 'back-to-bootrom' support for AArch64 The back-to-bootrom support for Rockchip is equivalent to an (assembly) implementation of setjmp/longjmp (i.e. it saves the stack-pointer, link-register and callee-saved registers). Up until now, this had only been implemented for AArch32 (i.e. ARMv7 or older), which puts the new ARMv8 devices (which boot in AArch64 mode) at a slight disadvantage. To allow use of the 'back-to-bootrom' feature on new devices (e.g. the RK3368), this commit adds an implementation for AArch64. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-06-22 22:05:38 +00:00
#if defined(CONFIG_ARM64)
.globl SAVE_SP_ADDR
SAVE_SP_ADDR:
.quad 0
ENTRY(save_boot_params)
sub sp, sp, #0x60
stp x29, x30, [sp, #0x50]
stp x27, x28, [sp, #0x40]
stp x25, x26, [sp, #0x30]
stp x23, x24, [sp, #0x20]
stp x21, x22, [sp, #0x10]
stp x19, x20, [sp, #0]
ldr x8, =SAVE_SP_ADDR
mov x9, sp
str x9, [x8]
b save_boot_params_ret /* back to my caller */
ENDPROC(save_boot_params)
.globl _back_to_bootrom_s
ENTRY(_back_to_bootrom_s)
ldr x0, =SAVE_SP_ADDR
ldr x0, [x0]
mov sp, x0
ldp x29, x30, [sp, #0x50]
ldp x27, x28, [sp, #0x40]
ldp x25, x26, [sp, #0x30]
ldp x23, x24, [sp, #0x20]
ldp x21, x22, [sp, #0x10]
ldp x19, x20, [sp]
add sp, sp, #0x60
mov x0, xzr
ret
ENDPROC(_back_to_bootrom_s)
#else
rockchip: rk3036: Add core Soc start-up code rk3036 only 4K size SRAM for SPL, so only support timer, uart, sdram driver in SPL stage, when finish initial sdram, back to bootrom.And in rk3036 sdmmc and debug uart use same iomux, so if you want to boot from sdmmc, you must disable debug uart. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed build error for chromebook_jerry, firefly-rk3288: Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - Fix build error for chromebook_jerry, firefly-rk3288
2015-11-17 06:20:27 +00:00
.globl SAVE_SP_ADDR
SAVE_SP_ADDR:
.word 0
/*
* void save_boot_params
*
* Save sp, lr, r1~r12
*/
ENTRY(save_boot_params)
push {r1-r12, lr}
ldr r0, =SAVE_SP_ADDR
str sp, [r0]
b save_boot_params_ret @ back to my caller
ENDPROC(save_boot_params)
rockchip: Print a message when returning to the bootrom At present if the return to bootrom fails (e.g. because you are not using the Rockchip's bootrom's pointer table in MMC) then the board prints SPL message and hangs. Print a message first if we can, to help in understanding what happened when it hangs. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Heiko Stuebner <heiko@sntech.de>
2017-04-15 19:11:31 +00:00
.globl _back_to_bootrom_s
ENTRY(_back_to_bootrom_s)
rockchip: rk3036: Add core Soc start-up code rk3036 only 4K size SRAM for SPL, so only support timer, uart, sdram driver in SPL stage, when finish initial sdram, back to bootrom.And in rk3036 sdmmc and debug uart use same iomux, so if you want to boot from sdmmc, you must disable debug uart. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed build error for chromebook_jerry, firefly-rk3288: Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - Fix build error for chromebook_jerry, firefly-rk3288
2015-11-17 06:20:27 +00:00
ldr r0, =SAVE_SP_ADDR
ldr sp, [r0]
mov r0, #0
pop {r1-r12, pc}
rockchip: Print a message when returning to the bootrom At present if the return to bootrom fails (e.g. because you are not using the Rockchip's bootrom's pointer table in MMC) then the board prints SPL message and hangs. Print a message first if we can, to help in understanding what happened when it hangs. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Heiko Stuebner <heiko@sntech.de>
2017-04-15 19:11:31 +00:00
ENDPROC(_back_to_bootrom_s)
rockchip: back-to-bootrom: add 'back-to-bootrom' support for AArch64 The back-to-bootrom support for Rockchip is equivalent to an (assembly) implementation of setjmp/longjmp (i.e. it saves the stack-pointer, link-register and callee-saved registers). Up until now, this had only been implemented for AArch32 (i.e. ARMv7 or older), which puts the new ARMv8 devices (which boot in AArch64 mode) at a slight disadvantage. To allow use of the 'back-to-bootrom' feature on new devices (e.g. the RK3368), this commit adds an implementation for AArch64. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-06-22 22:05:38 +00:00
#endif
Reference in a new issue Copy permalink