Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-06 13:14:27 +00:00
Code Issues Projects Releases Packages Wiki Activity
u-boot/arch/arm/mach-socfpga/include/mach/boot0.h

27 lines
501 B
C
Raw Normal View History

SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-06 21:58:06 +00:00
/* SPDX-License-Identifier: GPL-2.0+ */
ARM: socfpga: Add boot0 hook to prevent SPL corruption Valid Altera SoCFPGA preloader image must contain special data at offsets 0x40, 0x44, 0x48 and valid instructions at address 0x4c or 0x50. These addresses are by default used by U-Boot's vector table and a piece of reset handler, thus a valid preloader corrupts those addresses slightly. While this works most of the time, this can and does prevent the board from rebooting sometimes and triggering this issue may even depend on compiler. The problem is that when SoCFPGA performs warm reset, it checks the addresses 0x40..0x4b in SRAM for a valid preloader signature and header checksum. If those are found, it jumps to address 0x4c or 0x50 (this is unclear). These addresses are populated by the first few instructions of arch/arm/cpu/armv7/start.S: ffff0040 <data_abort>: ffff0040: ebfffffe bl ffff0040 <data_abort> ffff0044 <reset>: ffff0044: ea000012 b ffff0094 <save_boot_params> ffff0048 <save_boot_params_ret>: ffff0048: e10f0000 mrs r0, CPSR ffff004c: e200101f and r1, r0, #31 ffff0050: e331001a teq r1, #26 Without this patch, the CPU will enter the code at 0xffff004c or 0xffff0050 , at which point the value of r0 and r1 registers is undefined. Moreover, jumping directly to the preloader entry point at address 0xffff0000 will also fail, because address 0xffff004. is invalid and contains the preloader magic. Add BOOT0 hook which reserves the area at offset 0x40..0x5f and populates offset 0x50 with jump to the entry point. This way, the preloader signature is stored in reserved space and can not corrupt the SPL code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Stefan Roese <sr@denx.de> Tested-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-11-16 16:20:23 +00:00
/*
* Specialty padding for the Altera SoCFPGA preloader image
*/
#ifndef __BOOT0_H
#define __BOOT0_H
socfpga: boot0 hook: adjust to unified boot0 semantics With the updated boot0 semantics (i.e. giving the boot0-hook control over when and where the vector table is emitted), the boot0-hook for the socfpga needs to be adjusted. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-10 14:21:07 +00:00
_start:
ARM_VECTORS
ARM: socfpga: Add boot0 hook to prevent SPL corruption Valid Altera SoCFPGA preloader image must contain special data at offsets 0x40, 0x44, 0x48 and valid instructions at address 0x4c or 0x50. These addresses are by default used by U-Boot's vector table and a piece of reset handler, thus a valid preloader corrupts those addresses slightly. While this works most of the time, this can and does prevent the board from rebooting sometimes and triggering this issue may even depend on compiler. The problem is that when SoCFPGA performs warm reset, it checks the addresses 0x40..0x4b in SRAM for a valid preloader signature and header checksum. If those are found, it jumps to address 0x4c or 0x50 (this is unclear). These addresses are populated by the first few instructions of arch/arm/cpu/armv7/start.S: ffff0040 <data_abort>: ffff0040: ebfffffe bl ffff0040 <data_abort> ffff0044 <reset>: ffff0044: ea000012 b ffff0094 <save_boot_params> ffff0048 <save_boot_params_ret>: ffff0048: e10f0000 mrs r0, CPSR ffff004c: e200101f and r1, r0, #31 ffff0050: e331001a teq r1, #26 Without this patch, the CPU will enter the code at 0xffff004c or 0xffff0050 , at which point the value of r0 and r1 registers is undefined. Moreover, jumping directly to the preloader entry point at address 0xffff0000 will also fail, because address 0xffff004. is invalid and contains the preloader magic. Add BOOT0 hook which reserves the area at offset 0x40..0x5f and populates offset 0x50 with jump to the entry point. This way, the preloader signature is stored in reserved space and can not corrupt the SPL code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Stefan Roese <sr@denx.de> Tested-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-11-16 16:20:23 +00:00
#ifdef CONFIG_SPL_BUILD
ARM: socfpga: boot0 hook: remove macro from boot0 header file Commit ce62e57fc571 ("ARM: boot0 hook: remove macro, include whole header file") miss out cleaning macro in this header file, and this has broken implementation of a boot header capability in socfpga SPL. Remove the macro in this file, and recovering it back to proper functioning. Fixes: ce62e57fc571 ("ARM: boot0 hook: remove macro, include whole header file") Signed-off-by: Chee, Tien Fong <tien.fong.chee@intel.com>
2017-03-29 03:49:16 +00:00
.balignl 64,0xf33db33f;
.word 0x1337c0d3; /* SoCFPGA preloader validation word */
.word 0xc01df00d; /* Version, flags, length */
.word 0xcafec0d3; /* Checksum, zero-pad */
ARM: socfpga: Add boot0 hook to prevent SPL corruption Valid Altera SoCFPGA preloader image must contain special data at offsets 0x40, 0x44, 0x48 and valid instructions at address 0x4c or 0x50. These addresses are by default used by U-Boot's vector table and a piece of reset handler, thus a valid preloader corrupts those addresses slightly. While this works most of the time, this can and does prevent the board from rebooting sometimes and triggering this issue may even depend on compiler. The problem is that when SoCFPGA performs warm reset, it checks the addresses 0x40..0x4b in SRAM for a valid preloader signature and header checksum. If those are found, it jumps to address 0x4c or 0x50 (this is unclear). These addresses are populated by the first few instructions of arch/arm/cpu/armv7/start.S: ffff0040 <data_abort>: ffff0040: ebfffffe bl ffff0040 <data_abort> ffff0044 <reset>: ffff0044: ea000012 b ffff0094 <save_boot_params> ffff0048 <save_boot_params_ret>: ffff0048: e10f0000 mrs r0, CPSR ffff004c: e200101f and r1, r0, #31 ffff0050: e331001a teq r1, #26 Without this patch, the CPU will enter the code at 0xffff004c or 0xffff0050 , at which point the value of r0 and r1 registers is undefined. Moreover, jumping directly to the preloader entry point at address 0xffff0000 will also fail, because address 0xffff004. is invalid and contains the preloader magic. Add BOOT0 hook which reserves the area at offset 0x40..0x5f and populates offset 0x50 with jump to the entry point. This way, the preloader signature is stored in reserved space and can not corrupt the SPL code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Stefan Roese <sr@denx.de> Tested-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-11-16 16:20:23 +00:00
nop;
ARM: socfpga: Add boot trampoline for Arria10 The Arria10 uses slightly different boot image header than the Gen5 SoCs, in particular the header itself contains an offset from the start of the header to which the Arria10 jumps. This offset must not be negative, yet the header is placed at offset 0x40 of the bootable binary. Therefore, to jump into U-Boot, add a trampoline just past the Arria10 boot header and point to this trampoline at fixed offset from the header generated using the mkimage -T socfpgaimage_v1 . Note that it is not needed to jump back to offset 0x0 of the image, it is possible to jump directly at the reset label and save processing two instructions. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Chin Liang See <chin.liang.see@intel.com>
2018-04-15 11:15:33 +00:00
b reset; /* SoCFPGA Gen5 jumps here */
b reset; /* SoCFPGA Gen10 trampoline */
ARM: socfpga: boot0 hook: remove macro from boot0 header file Commit ce62e57fc571 ("ARM: boot0 hook: remove macro, include whole header file") miss out cleaning macro in this header file, and this has broken implementation of a boot header capability in socfpga SPL. Remove the macro in this file, and recovering it back to proper functioning. Fixes: ce62e57fc571 ("ARM: boot0 hook: remove macro, include whole header file") Signed-off-by: Chee, Tien Fong <tien.fong.chee@intel.com>
2017-03-29 03:49:16 +00:00
nop;
nop;
#endif
ARM: socfpga: Add boot0 hook to prevent SPL corruption Valid Altera SoCFPGA preloader image must contain special data at offsets 0x40, 0x44, 0x48 and valid instructions at address 0x4c or 0x50. These addresses are by default used by U-Boot's vector table and a piece of reset handler, thus a valid preloader corrupts those addresses slightly. While this works most of the time, this can and does prevent the board from rebooting sometimes and triggering this issue may even depend on compiler. The problem is that when SoCFPGA performs warm reset, it checks the addresses 0x40..0x4b in SRAM for a valid preloader signature and header checksum. If those are found, it jumps to address 0x4c or 0x50 (this is unclear). These addresses are populated by the first few instructions of arch/arm/cpu/armv7/start.S: ffff0040 <data_abort>: ffff0040: ebfffffe bl ffff0040 <data_abort> ffff0044 <reset>: ffff0044: ea000012 b ffff0094 <save_boot_params> ffff0048 <save_boot_params_ret>: ffff0048: e10f0000 mrs r0, CPSR ffff004c: e200101f and r1, r0, #31 ffff0050: e331001a teq r1, #26 Without this patch, the CPU will enter the code at 0xffff004c or 0xffff0050 , at which point the value of r0 and r1 registers is undefined. Moreover, jumping directly to the preloader entry point at address 0xffff0000 will also fail, because address 0xffff004. is invalid and contains the preloader magic. Add BOOT0 hook which reserves the area at offset 0x40..0x5f and populates offset 0x50 with jump to the entry point. This way, the preloader signature is stored in reserved space and can not corrupt the SPL code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Stefan Roese <sr@denx.de> Tested-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-11-16 16:20:23 +00:00
#endif /* __BOOT0_H */
Reference in a new issue Copy permalink