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u-boot/arch/arm/include/asm/arch-bcm281xx/sysmap.h

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SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-06 21:58:06 +00:00
/* SPDX-License-Identifier: GPL-2.0+ */
arch: bcm281xx: Initial commit of bcm281xx architecture code Add bcm281xx architecture support code including a clock framework and chip reset. Define register block base addresses for the bcm281xx architecture and create an empty gpio header file required when CONFIG_CMD_GPIO is set. Signed-off-by: Darwin Rambo <drambo@broadcom.com> Reviewed-by: Steve Rae <srae@broadcom.com> Reviewed-by: Tim Kryger <tkryger@linaro.org>
2014-02-11 19:06:34 +00:00
/*
* Copyright 2013 Broadcom Corporation.
*/
#ifndef __ARCH_BCM281XX_SYSMAP_H
#define BSC1_BASE_ADDR 0x3e016000
#define BSC2_BASE_ADDR 0x3e017000
#define BSC3_BASE_ADDR 0x3e018000
arm: bcm281xx: Add Ethernet Clock support Enable Ethernet clock when Broadcom StarFighter2 Ethernet block (CONFIG_BCM_SF2_ETH) is enabled. Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com> Signed-off-by: Steve Rae <srae@broadcom.com>
2014-08-02 03:37:15 +00:00
#define DWDMA_AHB_BASE_ADDR 0x38100000
#define ESUB_CLK_BASE_ADDR 0x38000000
#define ESW_CONTRL_BASE_ADDR 0x38200000
arch: bcm281xx: Initial commit of bcm281xx architecture code Add bcm281xx architecture support code including a clock framework and chip reset. Define register block base addresses for the bcm281xx architecture and create an empty gpio header file required when CONFIG_CMD_GPIO is set. Signed-off-by: Darwin Rambo <drambo@broadcom.com> Reviewed-by: Steve Rae <srae@broadcom.com> Reviewed-by: Tim Kryger <tkryger@linaro.org>
2014-02-11 19:06:34 +00:00
#define GPIO2_BASE_ADDR 0x35003000
bcm281xx: add support for "USB OTG clock" enable this clock with the following: clk_usb_otg_enable((void *)HSOTG_BASE_ADDR) Signed-off-by: Steve Rae <srae@broadcom.com> Reviewed-by: Felipe Balbi <balbi@ti.com>
2014-12-09 19:40:11 +00:00
#define HSOTG_BASE_ADDR 0x3f120000
#define HSOTG_CTRL_BASE_ADDR 0x3f130000
arch: bcm281xx: Initial commit of bcm281xx architecture code Add bcm281xx architecture support code including a clock framework and chip reset. Define register block base addresses for the bcm281xx architecture and create an empty gpio header file required when CONFIG_CMD_GPIO is set. Signed-off-by: Darwin Rambo <drambo@broadcom.com> Reviewed-by: Steve Rae <srae@broadcom.com> Reviewed-by: Tim Kryger <tkryger@linaro.org>
2014-02-11 19:06:34 +00:00
#define KONA_MST_CLK_BASE_ADDR 0x3f001000
#define KONA_SLV_CLK_BASE_ADDR 0x3e011000
#define PMU_BSC_BASE_ADDR 0x3500d000
#define PWRMGR_BASE_ADDR 0x35010000
#define SDIO1_BASE_ADDR 0x3f180000
#define SDIO2_BASE_ADDR 0x3f190000
#define SDIO3_BASE_ADDR 0x3f1a0000
#define SDIO4_BASE_ADDR 0x3f1b0000
#define SECWD_BASE_ADDR 0x3500c000
#define SECWD2_BASE_ADDR 0x35002f40
#define TIMER_BASE_ADDR 0x3e00d000
usb: gadget: bcm_udc_otg files Add the required files for the Broadcom UDC OTG interface. Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com> Signed-off-by: Steve Rae <srae@broadcom.com>
2015-07-09 21:26:39 +00:00
#define HSOTG_DCTL_OFFSET 0x00000804
#define HSOTG_DCTL_SFTDISCON_MASK 0x00000002
#define HSOTG_CTRL_PHY_P1CTL_OFFSET 0x00000008
#define HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK 0x00000002
#define HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK 0x00000001
arch: bcm281xx: Initial commit of bcm281xx architecture code Add bcm281xx architecture support code including a clock framework and chip reset. Define register block base addresses for the bcm281xx architecture and create an empty gpio header file required when CONFIG_CMD_GPIO is set. Signed-off-by: Darwin Rambo <drambo@broadcom.com> Reviewed-by: Steve Rae <srae@broadcom.com> Reviewed-by: Tim Kryger <tkryger@linaro.org>
2014-02-11 19:06:34 +00:00
#endif
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