powerpc/85xx: Add P5040 processor support
Add support for the Freescale P5040 SOC, which is similar to the P5020.
Features of the P5040 are:
Four P5040 single-threaded e5500 cores built
Up to 2.4 GHz with 64-bit ISA support
Three levels of instruction: user, supervisor, hypervisor
CoreNet platform cache (CPC)
2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric
Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
support Up to 1600MT/s
Memory pre-fetch engine
DPAA incorporating acceleration for the following functions
Packet parsing, classification, and distribution (FMAN)
Queue management for scheduling, packet sequencing and
congestion management (QMAN)
Hardware buffer management for buffer allocation and
de-allocation (BMAN)
Cryptography acceleration (SEC 5.2) at up to 40 Gbps SerDes
20 lanes at up to 5 Gbps
Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces
Two 10 Gbps Ethernet MACs
Ten 1 Gbps Ethernet MACs
High-speed peripheral interfaces
Two PCI Express 2.0/3.0 controllers
Additional peripheral interfaces
Two serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHY
Enhanced secure digital host controller (SD/MMC/eMMC)
Enhanced serial peripheral interface (eSPI)
Two I2C controllers
Four UARTs
Integrated flash controller supporting NAND and NOR flash
DMA
Dual four channel
Support for hardware virtualization and partitioning enforcement
Extra privileged level for hypervisor support
QorIQ Trust Architecture 1.1
Secure boot, secure debug, tamper detection, volatile key storage
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-05 11:09:19 +00:00
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/*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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*
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2013-07-08 07:37:19 +00:00
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* SPDX-License-Identifier: GPL-2.0+
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powerpc/85xx: Add P5040 processor support
Add support for the Freescale P5040 SOC, which is similar to the P5020.
Features of the P5040 are:
Four P5040 single-threaded e5500 cores built
Up to 2.4 GHz with 64-bit ISA support
Three levels of instruction: user, supervisor, hypervisor
CoreNet platform cache (CPC)
2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric
Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
support Up to 1600MT/s
Memory pre-fetch engine
DPAA incorporating acceleration for the following functions
Packet parsing, classification, and distribution (FMAN)
Queue management for scheduling, packet sequencing and
congestion management (QMAN)
Hardware buffer management for buffer allocation and
de-allocation (BMAN)
Cryptography acceleration (SEC 5.2) at up to 40 Gbps SerDes
20 lanes at up to 5 Gbps
Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces
Two 10 Gbps Ethernet MACs
Ten 1 Gbps Ethernet MACs
High-speed peripheral interfaces
Two PCI Express 2.0/3.0 controllers
Additional peripheral interfaces
Two serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHY
Enhanced secure digital host controller (SD/MMC/eMMC)
Enhanced serial peripheral interface (eSPI)
Two I2C controllers
Four UARTs
Integrated flash controller supporting NAND and NOR flash
DMA
Dual four channel
Support for hardware virtualization and partitioning enforcement
Extra privileged level for hypervisor support
QorIQ Trust Architecture 1.1
Secure boot, secure debug, tamper detection, volatile key storage
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-05 11:09:19 +00:00
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*/
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#include <common.h>
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#include <asm/fsl_portals.h>
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#include <asm/fsl_liodn.h>
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#ifdef CONFIG_SYS_DPAA_QBMAN
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struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
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/* dqrr liodn, frame data liodn, liodn off, sdest */
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SET_QP_INFO(1, 2, 1, 0),
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SET_QP_INFO(3, 4, 2, 1),
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SET_QP_INFO(5, 6, 3, 2),
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SET_QP_INFO(7, 8, 4, 3),
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SET_QP_INFO(9, 10, 5, 0),
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SET_QP_INFO(11, 12, 6, 1),
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SET_QP_INFO(13, 14, 7, 2),
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SET_QP_INFO(15, 16, 8, 3),
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SET_QP_INFO(17, 18, 9, 0), /* for now, set sdest to 0 */
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SET_QP_INFO(19, 20, 10, 0), /* for now, set sdest to 0 */
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};
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#endif
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struct liodn_id_table liodn_tbl[] = {
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#ifdef CONFIG_SYS_DPAA_QBMAN
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SET_QMAN_LIODN(31),
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SET_BMAN_LIODN(32),
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#endif
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SET_SDHC_LIODN(1, 64),
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SET_USB_LIODN(1, "fsl-usb2-mph", 93),
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SET_USB_LIODN(2, "fsl-usb2-dr", 94),
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SET_SATA_LIODN(1, 95),
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SET_SATA_LIODN(2, 96),
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SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 195),
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SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 196),
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SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 197),
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SET_DMA_LIODN(1, 193),
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SET_DMA_LIODN(2, 194),
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};
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int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
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#ifdef CONFIG_SYS_DPAA_FMAN
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struct liodn_id_table fman1_liodn_tbl[] = {
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SET_FMAN_RX_1G_LIODN(1, 0, 6),
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SET_FMAN_RX_1G_LIODN(1, 1, 7),
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SET_FMAN_RX_1G_LIODN(1, 2, 8),
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SET_FMAN_RX_1G_LIODN(1, 3, 9),
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SET_FMAN_RX_1G_LIODN(1, 4, 10),
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SET_FMAN_RX_10G_LIODN(1, 0, 11),
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};
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int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
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#if (CONFIG_SYS_NUM_FMAN == 2)
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struct liodn_id_table fman2_liodn_tbl[] = {
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SET_FMAN_RX_1G_LIODN(2, 0, 12),
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SET_FMAN_RX_1G_LIODN(2, 1, 13),
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SET_FMAN_RX_1G_LIODN(2, 2, 14),
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SET_FMAN_RX_1G_LIODN(2, 3, 15),
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SET_FMAN_RX_1G_LIODN(2, 4, 16),
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SET_FMAN_RX_10G_LIODN(2, 0, 17),
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};
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int fman2_liodn_tbl_sz = ARRAY_SIZE(fman2_liodn_tbl);
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#endif
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#endif
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struct liodn_id_table sec_liodn_tbl[] = {
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SET_SEC_JR_LIODN_ENTRY(0, 129, 130),
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SET_SEC_JR_LIODN_ENTRY(1, 131, 132),
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SET_SEC_JR_LIODN_ENTRY(2, 133, 134),
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SET_SEC_JR_LIODN_ENTRY(3, 135, 136),
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SET_SEC_RTIC_LIODN_ENTRY(a, 89),
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SET_SEC_RTIC_LIODN_ENTRY(b, 90),
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SET_SEC_RTIC_LIODN_ENTRY(c, 91),
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SET_SEC_RTIC_LIODN_ENTRY(d, 92),
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SET_SEC_DECO_LIODN_ENTRY(0, 139, 140),
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SET_SEC_DECO_LIODN_ENTRY(1, 141, 142),
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SET_SEC_DECO_LIODN_ENTRY(2, 143, 144),
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SET_SEC_DECO_LIODN_ENTRY(3, 145, 146),
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};
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int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
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#ifdef CONFIG_SYS_FSL_RAID_ENGINE
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struct liodn_id_table raide_liodn_tbl[] = {
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SET_RAID_ENGINE_JQ_LIODN_ENTRY(0, 0, 60),
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SET_RAID_ENGINE_JQ_LIODN_ENTRY(0, 1, 61),
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SET_RAID_ENGINE_JQ_LIODN_ENTRY(1, 0, 62),
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SET_RAID_ENGINE_JQ_LIODN_ENTRY(1, 1, 63),
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};
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int raide_liodn_tbl_sz = ARRAY_SIZE(raide_liodn_tbl);
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#endif
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struct liodn_id_table liodn_bases[] = {
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[FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(64, 101),
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#ifdef CONFIG_SYS_DPAA_FMAN
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[FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32),
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#endif
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#if (CONFIG_SYS_NUM_FMAN == 2)
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[FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(160),
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#endif
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#ifdef CONFIG_SYS_FSL_RAID_ENGINE
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[FSL_HW_PORTAL_RAID_ENGINE] = SET_LIODN_BASE_1(49),
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#endif
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};
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