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u-boot/arch/x86/include/asm/cb_sysinfo.h

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SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-06 21:58:06 +00:00
/* SPDX-License-Identifier: BSD-3-Clause */
x86: Import code from coreboot's libpayload to parse the coreboot table This change also forces the lib_sysinfo structure to be in the .data section. Otherwise it ends up in the .bss section. U-boot assumes that it doesn't need to copy it over during relocation, and instead fills that whole section with zeroes. If we really were booting from ROM that would be appropriate, but we need some information from the coreboot tables (memory size) before then and have to fill that structure before relocation. We skirt u-boot's assumption by putting this in .data where it assumes there is still read only but non-zero data. Signed-off-by: Gabe Black <gabeblack@chromium.org>
2011-12-05 12:09:22 +00:00
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*/
#ifndef _COREBOOT_SYSINFO_H
#define _COREBOOT_SYSINFO_H
x86: Move asm/arch-coreboot/tables.h to a common place Move asm/arch-coreboot/tables.h to asm/coreboot_tables.h so that coreboot table definitions can be used by other x86 builds. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-28 06:57:55 +00:00
#include <asm/coreboot_tables.h>
x86: Import code from coreboot's libpayload to parse the coreboot table This change also forces the lib_sysinfo structure to be in the .data section. Otherwise it ends up in the .bss section. U-boot assumes that it doesn't need to copy it over during relocation, and instead fills that whole section with zeroes. If we really were booting from ROM that would be appropriate, but we need some information from the coreboot tables (memory size) before then and have to fill that structure before relocation. We skirt u-boot's assumption by putting this in .data where it assumes there is still read only but non-zero data. Signed-off-by: Gabe Black <gabeblack@chromium.org>
2011-12-05 12:09:22 +00:00
x86: coreboot: Increase memrange entry number to 32 Increase lib_sysinfo memrange entry number to 32 to sync with coreboot. This allows a complete E820 table to be reported to the kernel, as on some platforms (eg: Bayley Bay) having only 16 entires does not cover all the memory ranges. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-13 07:29:08 +00:00
/* Maximum number of memory range definitions */
#define SYSINFO_MAX_MEM_RANGES 32
x86: coreboot: Decode additional coreboot sysinfo tags Add support for decoding tags for GPIOs, compile/build info, cbmem and other features. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-10-12 18:48:46 +00:00
/* Allow a maximum of 8 GPIOs */
x86: coreboot: Increase memrange entry number to 32 Increase lib_sysinfo memrange entry number to 32 to sync with coreboot. This allows a complete E820 table to be reported to the kernel, as on some platforms (eg: Bayley Bay) having only 16 entires does not cover all the memory ranges. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-13 07:29:08 +00:00
#define SYSINFO_MAX_GPIOS 8
x86: coreboot: Update parsing of the latest sysinfo Quite a few new tag types have been added over the years. Bring these into U-Boot so that all required tags can be parsed. Add a proper comment to struct sysinfo_t while we are here, since many of the meanings are not obvious. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-15 05:00:22 +00:00
/* Up to 10 MAC addresses */
#define SYSINFO_MAX_MACS 10
x86: Import code from coreboot's libpayload to parse the coreboot table This change also forces the lib_sysinfo structure to be in the .data section. Otherwise it ends up in the .bss section. U-boot assumes that it doesn't need to copy it over during relocation, and instead fills that whole section with zeroes. If we really were booting from ROM that would be appropriate, but we need some information from the coreboot tables (memory size) before then and have to fill that structure before relocation. We skirt u-boot's assumption by putting this in .data where it assumes there is still read only but non-zero data. Signed-off-by: Gabe Black <gabeblack@chromium.org>
2011-12-05 12:09:22 +00:00
x86: coreboot: Update parsing of the latest sysinfo Quite a few new tag types have been added over the years. Bring these into U-Boot so that all required tags can be parsed. Add a proper comment to struct sysinfo_t while we are here, since many of the meanings are not obvious. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-15 05:00:22 +00:00
/**
* struct sysinfo_t - Information passed to U-Boot from coreboot
*
* Coreboot passes on a lot of information using a list of individual data
* structures identified by a numeric tag. These are parsed in U-Boot to produce
* this struct. Some of the pointers here point back to the tagged data
* structure, since it is assumed to remain around while U-Boot is running.
*
* The 'cbsysinfo' command can display this information.
*
* @cpu_khz: CPU frequence in KHz (e.g. 1100000)
* @serial: Pointer to the serial information, NULL if none
* @ser_ioport: Not actually provided by a tag and not used on modern hardware,
* which typicaally uses a memory-mapped port
* @ser_base: Not used at all, but present to match up with the coreboot data
* structure
* @n_memranges: Number of memory ranges
* @memrange: List of memory ranges:
* @base: Base address of range
* @size: Size of range in bytes
* @type: Type of range (CB_MEM_RAM, etc.)
* @option_table: Provides a pointer to the CMOS RAM options table, which
* indicates which options are available. The header is followed by a list
* of struct cb_cmos_entries records, so that an option can be found from
* its name. This is not used in U-Boot. NULL if not present
* @cmos_range_start: Start bit of the CMOS checksum range (in fact this must
* be a multiple of 8)
* @cmos_range_end: End bit of the CMOS checksum range (multiple of 8). This is
* the inclusive end.
* @cmos_checksum_location: Location of checksum, multiplied by 8. This is the
* byte offset into the CMOS RAM of the first checksum byte. The second one
* follows immediately. The checksum is a simple 16-bit sum of all the
* bytes from offset cmos_range_start / 8 to cmos_range_end / 8, inclusive,
* in big-endian format (so sum >> 8 is stored in the first byte).
* @vbnv_start: Start offset of CMOS RAM used for Chromium OS verified boot
* (typically 0x34)
* @vbnv_size: Number of bytes used by Chromium OS verified boot (typically
* 0x10)
* @extra_version: Extra version information, typically ""
* @build: Build date, e.g. "Wed Nov 18 02:51:58 UTC 2020"
* @compile_time: Compilation time, e.g. "02:51:58"
* @compile_by: Who compiled coreboot (never set?)
* @compile_host: Name of the machine that compiled coreboot (never set?)
* @compile_domain: Domain name of the machine that compiled coreboot (never
* set?)
* @compiler: Name of the compiler used to build coreboot (never set?)
* @linker: Name of the linker used to build coreboot (never set?)
* @assembler: Name of the assembler used to build coreboot (never set?)
* @cb_version: Coreboot version string, e.g. v1.9308_26_0.0.22-2599-g232f22c75d
* @framebuffer: Address of framebuffer tag, or NULL if none. See
* struct cb_framebuffer for the definition
* @num_gpios: Number of verified-boot GPIOs
* @gpios: List of GPIOs:
* @port: GPIO number, or 0xffffffff if not a GPIO
* @polarity: CB_GPIO_ACTIVE_LOW or CB_GPIO_ACTIVE_HIGH
* @value: Value of GPIO (0 or 1)
* @name: Name of GPIO
*
* A typical list is:
* id: port polarity val name
* 0: - active-high 1 write protect
* 1: - active-high 0 recovery
* 2: - active-high 1 lid
* 3: - active-high 0 power
* 4: - active-high 0 oprom
* 5: 29 active-high 0 EC in RW
*
* @num_macs: Number of MAC addresses
* @macs: List of MAC addresses
* @serialno: Serial number, or NULL (never set?)
* @mbtable: Address of the multiboot table, or NULL. This is a
* struct multiboot_header, not used in U-Boot
* @header: Address of header, if there is a CB_TAG_FORWARD, else NULL
* @mainboard: Pointer to mainboard info or NULL. Typically the vendor is
* "Google" and the part number is ""
* @vboot_handoff: Pointer to Chromium OS verified boot hand-off information.
* This is struct vboot_handoff, providing access to internal information
* generated by coreboot when this is being used
* @vboot_handoff_size: Size of hand-off information (typically 0xc0c)
* @vdat_addr: Pointer to Chromium OS verified boot data, which uses
* struct chromeos_acpi. It sits in the Intel Global NVS struct, after the
* first 0x100 bytes
* @vdat_size: Size of this data, typically 0xf00
* @smbios_start: Address of SMBIOS tables
* @smbios_size: Size of SMBIOS tables (e.g. 0x800)
* @x86_rom_var_mtrr_index: MTRR number used for ROM caching. Not used in U-Boot
* @tstamp_table: Pointer to timestamp_table, struct timestamp_table
* @cbmem_cons: Pointer to the console dump, struct cbmem_console. This provides
* access to the console output generated by coreboot, typically about 64KB
* and mostly PCI enumeration info
* @mrc_cache: Pointer to memory-reference-code cache, typically NULL
* acpi_gnvs: @Pointer to Intel Global NVS struct, see struct acpi_global_nvs
* @board_id: Board ID indicating the board variant, typically 0xffffffff
* @ram_code: RAM code indicating the SDRAM type, typically 0xffffffff
* @wifi_calibration: WiFi calibration info, NULL if none
* @ramoops_buffer: Address of kernel Ramoops buffer
* @ramoops_buffer_size: Sizeof of Ramoops buffer, typically 1MB
* @spi_flash: Information about SPI flash:
* @size: Size in bytes, e.g. 16MB
* @sector_size; Sector size of flash device, e.g. 4KB
* @erase_cmd: Command used to erase flash, or 0 if not used
* @fmap_offset: SPI-flash offset of the flash map (FMAP) table. This has a
* __FMAP__ header. It provides information about the different top-level
* sections in the SPI flash, e.g. 0x204000
* @cbfs_offset: SPI-flash offset of the Coreboot Filesystem (CBFS) used for
* read-only data, e.g. 0x205000. This is typically called 'COREBOOT' in
* the flash map. It holds various coreboot binaries as well as
* video-configuration files and graphics data for the Chromium OS
* verified boot user interface.
* @cbfs_size: Size of CBFS, e.g. 0x17b000
* @boot_media_size; Size of boot media (i.e. SPI flash), e.g. 16MB
* @mtc_start; Start of MTC region (Nvidia private data), 0 if not used. See
* https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2013.04/src/soc/nvidia/tegra210/mtc.c
* @mtc_size: Size of MTC region
* @chromeos_vpd: Chromium OS Vital Product Data region, typically NULL, meaning
* not used
*/
x86: Import code from coreboot's libpayload to parse the coreboot table This change also forces the lib_sysinfo structure to be in the .data section. Otherwise it ends up in the .bss section. U-boot assumes that it doesn't need to copy it over during relocation, and instead fills that whole section with zeroes. If we really were booting from ROM that would be appropriate, but we need some information from the coreboot tables (memory size) before then and have to fill that structure before relocation. We skirt u-boot's assumption by putting this in .data where it assumes there is still read only but non-zero data. Signed-off-by: Gabe Black <gabeblack@chromium.org>
2011-12-05 12:09:22 +00:00
struct sysinfo_t {
x86: coreboot: Update parsing of the latest sysinfo Quite a few new tag types have been added over the years. Bring these into U-Boot so that all required tags can be parsed. Add a proper comment to struct sysinfo_t while we are here, since many of the meanings are not obvious. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-15 05:00:22 +00:00
unsigned int cpu_khz;
struct cb_serial *serial;
unsigned short ser_ioport;
unsigned long ser_base; // for mmapped serial
x86: Import code from coreboot's libpayload to parse the coreboot table This change also forces the lib_sysinfo structure to be in the .data section. Otherwise it ends up in the .bss section. U-boot assumes that it doesn't need to copy it over during relocation, and instead fills that whole section with zeroes. If we really were booting from ROM that would be appropriate, but we need some information from the coreboot tables (memory size) before then and have to fill that structure before relocation. We skirt u-boot's assumption by putting this in .data where it assumes there is still read only but non-zero data. Signed-off-by: Gabe Black <gabeblack@chromium.org>
2011-12-05 12:09:22 +00:00
int n_memranges;
x86: coreboot: Update parsing of the latest sysinfo Quite a few new tag types have been added over the years. Bring these into U-Boot so that all required tags can be parsed. Add a proper comment to struct sysinfo_t while we are here, since many of the meanings are not obvious. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-15 05:00:22 +00:00
x86: Import code from coreboot's libpayload to parse the coreboot table This change also forces the lib_sysinfo structure to be in the .data section. Otherwise it ends up in the .bss section. U-boot assumes that it doesn't need to copy it over during relocation, and instead fills that whole section with zeroes. If we really were booting from ROM that would be appropriate, but we need some information from the coreboot tables (memory size) before then and have to fill that structure before relocation. We skirt u-boot's assumption by putting this in .data where it assumes there is still read only but non-zero data. Signed-off-by: Gabe Black <gabeblack@chromium.org>
2011-12-05 12:09:22 +00:00
struct memrange {
unsigned long long base;
unsigned long long size;
unsigned int type;
} memrange[SYSINFO_MAX_MEM_RANGES];
x86: coreboot: Update parsing of the latest sysinfo Quite a few new tag types have been added over the years. Bring these into U-Boot so that all required tags can be parsed. Add a proper comment to struct sysinfo_t while we are here, since many of the meanings are not obvious. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-15 05:00:22 +00:00
struct cb_cmos_option_table *option_table;
x86: Import code from coreboot's libpayload to parse the coreboot table This change also forces the lib_sysinfo structure to be in the .data section. Otherwise it ends up in the .bss section. U-boot assumes that it doesn't need to copy it over during relocation, and instead fills that whole section with zeroes. If we really were booting from ROM that would be appropriate, but we need some information from the coreboot tables (memory size) before then and have to fill that structure before relocation. We skirt u-boot's assumption by putting this in .data where it assumes there is still read only but non-zero data. Signed-off-by: Gabe Black <gabeblack@chromium.org>
2011-12-05 12:09:22 +00:00
u32 cmos_range_start;
u32 cmos_range_end;
u32 cmos_checksum_location;
x86: coreboot: Decode additional coreboot sysinfo tags Add support for decoding tags for GPIOs, compile/build info, cbmem and other features. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-10-12 18:48:46 +00:00
u32 vbnv_start;
u32 vbnv_size;
char *version;
char *extra_version;
char *build;
char *compile_time;
char *compile_by;
char *compile_host;
char *compile_domain;
char *compiler;
char *linker;
char *assembler;
x86: Import code from coreboot's libpayload to parse the coreboot table This change also forces the lib_sysinfo structure to be in the .data section. Otherwise it ends up in the .bss section. U-boot assumes that it doesn't need to copy it over during relocation, and instead fills that whole section with zeroes. If we really were booting from ROM that would be appropriate, but we need some information from the coreboot tables (memory size) before then and have to fill that structure before relocation. We skirt u-boot's assumption by putting this in .data where it assumes there is still read only but non-zero data. Signed-off-by: Gabe Black <gabeblack@chromium.org>
2011-12-05 12:09:22 +00:00
x86: coreboot: Update parsing of the latest sysinfo Quite a few new tag types have been added over the years. Bring these into U-Boot so that all required tags can be parsed. Add a proper comment to struct sysinfo_t while we are here, since many of the meanings are not obvious. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-15 05:00:22 +00:00
char *cb_version;
x86: Import code from coreboot's libpayload to parse the coreboot table This change also forces the lib_sysinfo structure to be in the .data section. Otherwise it ends up in the .bss section. U-boot assumes that it doesn't need to copy it over during relocation, and instead fills that whole section with zeroes. If we really were booting from ROM that would be appropriate, but we need some information from the coreboot tables (memory size) before then and have to fill that structure before relocation. We skirt u-boot's assumption by putting this in .data where it assumes there is still read only but non-zero data. Signed-off-by: Gabe Black <gabeblack@chromium.org>
2011-12-05 12:09:22 +00:00
struct cb_framebuffer *framebuffer;
x86: coreboot: Decode additional coreboot sysinfo tags Add support for decoding tags for GPIOs, compile/build info, cbmem and other features. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-10-12 18:48:46 +00:00
int num_gpios;
struct cb_gpio gpios[SYSINFO_MAX_GPIOS];
x86: coreboot: Update parsing of the latest sysinfo Quite a few new tag types have been added over the years. Bring these into U-Boot so that all required tags can be parsed. Add a proper comment to struct sysinfo_t while we are here, since many of the meanings are not obvious. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-15 05:00:22 +00:00
int num_macs;
struct mac_address macs[SYSINFO_MAX_MACS];
char *serialno;
unsigned long *mbtable; /** Pointer to the multiboot table */
x86: coreboot: Decode additional coreboot sysinfo tags Add support for decoding tags for GPIOs, compile/build info, cbmem and other features. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-10-12 18:48:46 +00:00
x86: coreboot: Update parsing of the latest sysinfo Quite a few new tag types have been added over the years. Bring these into U-Boot so that all required tags can be parsed. Add a proper comment to struct sysinfo_t while we are here, since many of the meanings are not obvious. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-15 05:00:22 +00:00
struct cb_header *header;
struct cb_mainboard *mainboard;
void *vboot_handoff;
u32 vboot_handoff_size;
x86: coreboot: Decode additional coreboot sysinfo tags Add support for decoding tags for GPIOs, compile/build info, cbmem and other features. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-10-12 18:48:46 +00:00
void *vdat_addr;
u32 vdat_size;
x86: coreboot: add SMBIOS cbmem entry parsing Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-05-14 13:16:22 +00:00
u64 smbios_start;
u32 smbios_size;
x86: coreboot: Decode additional coreboot sysinfo tags Add support for decoding tags for GPIOs, compile/build info, cbmem and other features. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-10-12 18:48:46 +00:00
x86: coreboot: Update parsing of the latest sysinfo Quite a few new tag types have been added over the years. Bring these into U-Boot so that all required tags can be parsed. Add a proper comment to struct sysinfo_t while we are here, since many of the meanings are not obvious. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-15 05:00:22 +00:00
int x86_rom_var_mtrr_index;
void *tstamp_table;
void *cbmem_cons;
void *mrc_cache;
void *acpi_gnvs;
u32 board_id;
u32 ram_code;
void *wifi_calibration;
u64 ramoops_buffer;
u32 ramoops_buffer_size;
struct {
u32 size;
u32 sector_size;
u32 erase_cmd;
} spi_flash;
u64 fmap_offset;
u64 cbfs_offset;
u64 cbfs_size;
u64 boot_media_size;
u64 mtc_start;
u32 mtc_size;
void *chromeos_vpd;
x86: Import code from coreboot's libpayload to parse the coreboot table This change also forces the lib_sysinfo structure to be in the .data section. Otherwise it ends up in the .bss section. U-boot assumes that it doesn't need to copy it over during relocation, and instead fills that whole section with zeroes. If we really were booting from ROM that would be appropriate, but we need some information from the coreboot tables (memory size) before then and have to fill that structure before relocation. We skirt u-boot's assumption by putting this in .data where it assumes there is still read only but non-zero data. Signed-off-by: Gabe Black <gabeblack@chromium.org>
2011-12-05 12:09:22 +00:00
};
extern struct sysinfo_t lib_sysinfo;
x86: Move sysinfo related to sysinfo.h coreboot_tables.h should not include sysinfo related stuff. Move those to asm/arch-coreboot/sysinfo.h. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-28 06:57:56 +00:00
int get_coreboot_info(struct sysinfo_t *info);
x86: Import code from coreboot's libpayload to parse the coreboot table This change also forces the lib_sysinfo structure to be in the .data section. Otherwise it ends up in the .bss section. U-boot assumes that it doesn't need to copy it over during relocation, and instead fills that whole section with zeroes. If we really were booting from ROM that would be appropriate, but we need some information from the coreboot tables (memory size) before then and have to fill that structure before relocation. We skirt u-boot's assumption by putting this in .data where it assumes there is still read only but non-zero data. Signed-off-by: Gabe Black <gabeblack@chromium.org>
2011-12-05 12:09:22 +00:00
#endif
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