u-boot/arch/mips/dts/brcm,bcm63268.dtsi

/*
 * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <dt-bindings/clock/bcm63268-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/power-domain/bcm63268-power-domain.h>
#include <dt-bindings/reset/bcm63268-reset.h>
#include "skeleton.dtsi"

/ {
	compatible = "brcm,bcm63268";

	aliases {
		spi0 = &lsspi;
		spi1 = &hsspi;
	};

	cpus {
		reg = <0x10000000 0x4>;
		#address-cells = <1>;
		#size-cells = <0>;
		u-boot,dm-pre-reloc;

		cpu@0 {
			compatible = "brcm,bcm63268-cpu", "mips,mips4Kc";
			device_type = "cpu";
			reg = <0>;
			u-boot,dm-pre-reloc;
		};

		cpu@1 {
			compatible = "brcm,bcm63268-cpu", "mips,mips4Kc";
			device_type = "cpu";
			reg = <1>;
			u-boot,dm-pre-reloc;
		};
	};

	clocks {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		u-boot,dm-pre-reloc;

		hsspi_pll: hsspi-pll {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <400000000>;
		};

		periph_osc: periph-osc {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <50000000>;
			u-boot,dm-pre-reloc;
		};

		periph_clk: periph-clk {
			compatible = "brcm,bcm6345-clk";
			reg = <0x10000004 0x4>;
			#clock-cells = <1>;
		};

		timer_clk: timer-clk {
			compatible = "brcm,bcm6345-clk";
			reg = <0x100000ac 0x4>;
			#clock-cells = <1>;
		};
	};

	ubus {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		u-boot,dm-pre-reloc;

		pll_cntl: syscon@10000008 {
			compatible = "syscon";
			reg = <0x10000008 0x4>;
		};

		syscon-reboot {
			compatible = "syscon-reboot";
			regmap = <&pll_cntl>;
			offset = <0x0>;
			mask = <0x1>;
		};

		periph_rst: reset-controller@10000010 {
			compatible = "brcm,bcm6345-reset";
			reg = <0x10000010 0x4>;
			#reset-cells = <1>;
		};

		wdt: watchdog@1000009c {
			compatible = "brcm,bcm6345-wdt";
			reg = <0x1000009c 0xc>;
			clocks = <&periph_osc>;
		};

		wdt-reboot {
			compatible = "wdt-reboot";
			wdt = <&wdt>;
		};

		gpio1: gpio-controller@100000c0 {
			compatible = "brcm,bcm6345-gpio";
			reg = <0x100000c0 0x4>, <0x100000c8 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			ngpios = <20>;

			status = "disabled";
		};

		gpio0: gpio-controller@100000c4 {
			compatible = "brcm,bcm6345-gpio";
			reg = <0x100000c4 0x4>, <0x100000cc 0x4>;
			gpio-controller;
			#gpio-cells = <2>;

			status = "disabled";
		};

		uart0: serial@10000180 {
			compatible = "brcm,bcm6345-uart";
			reg = <0x10000180 0x18>;
			clocks = <&periph_osc>;

			status = "disabled";
		};

		uart1: serial@100001a0 {
			compatible = "brcm,bcm6345-uart";
			reg = <0x100001a0 0x18>;
			clocks = <&periph_osc>;

			status = "disabled";
		};

		periph_pwr: power-controller@1000184c {
			compatible = "brcm,bcm6328-power-domain";
			reg = <0x1000184c 0x4>;
			#power-domain-cells = <1>;
		};

		lsspi: spi@10000800 {
			compatible = "brcm,bcm6358-spi";
			reg = <0x10000800 0x70c>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&periph_clk BCM63268_CLK_SPI>;
			resets = <&periph_rst BCM63268_RST_SPI>;
			spi-max-frequency = <20000000>;
			num-cs = <8>;

			status = "disabled";
		};

		hsspi: spi@10001000 {
			compatible = "brcm,bcm6328-hsspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x10001000 0x600>;
			clocks = <&periph_clk BCM63268_CLK_HSSPI>, <&hsspi_pll>;
			clock-names = "hsspi", "pll";
			resets = <&periph_rst BCM63268_RST_SPI>;
			spi-max-frequency = <50000000>;
			num-cs = <8>;

			status = "disabled";
		};

		leds: led-controller@10001900 {
			compatible = "brcm,bcm6328-leds";
			reg = <0x10001900 0x24>;
			#address-cells = <1>;
			#size-cells = <0>;

			status = "disabled";
		};

		memory-controller@10003000 {
			compatible = "brcm,bcm6328-mc";
			reg = <0x10003000 0x894>;
			u-boot,dm-pre-reloc;
		};
	};
};