2020-01-10 14:51:48 +00:00
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) 2019
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* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
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*/
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2022-11-07 21:22:36 +00:00
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#include <dt-bindings/memory/imxrt-sdram.h>
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#include "imxrt1050-pinfunc.h"
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2020-01-10 14:51:48 +00:00
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/ {
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2022-11-07 21:22:36 +00:00
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aliases {
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display0 = &lcdif;
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usbphy0 = &usbphy1;
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};
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2020-01-10 14:51:48 +00:00
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chosen {
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u-boot,dm-spl;
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2022-11-07 21:22:36 +00:00
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tick-timer = &gpt;
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2020-01-10 14:51:48 +00:00
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};
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2021-05-16 21:57:00 +00:00
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clocks {
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u-boot,dm-spl;
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};
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soc {
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u-boot,dm-spl;
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2022-11-07 21:22:36 +00:00
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usbphy1: usbphy@400d9000 {
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compatible = "fsl,imxrt-usbphy";
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reg = <0x400d9000 0x1000>;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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};
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usbmisc: usbmisc@402e0800 {
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#index-cells = <1>;
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compatible = "fsl,imxrt-usbmisc";
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reg = <0x402e0800 0x200>;
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clocks = <&clks IMXRT1050_CLK_USBOH3>;
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};
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usbotg1: usb@402e0000 {
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compatible = "fsl,imxrt-usb", "fsl,imx27-usb";
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reg = <0x402e0000 0x200>;
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interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMXRT1050_CLK_USBOH3>;
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fsl,usbphy = <&usbphy1>;
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fsl,usbmisc = <&usbmisc 0>;
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ahb-burst-config = <0x0>;
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tx-burst-size-dword = <0x10>;
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rx-burst-size-dword = <0x10>;
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status = "disabled";
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};
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lcdif: lcdif@402b8000 {
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compatible = "fsl,imxrt-lcdif";
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reg = <0x402b8000 0x4000>;
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interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMXRT1050_CLK_LCDIF_PIX>,
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<&clks IMXRT1050_CLK_LCDIF_APB>;
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clock-names = "pix", "axi";
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assigned-clocks = <&clks IMXRT1050_CLK_LCDIF_SEL>;
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assigned-clock-parents = <&clks IMXRT1050_CLK_PLL5_VIDEO>;
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status = "disabled";
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};
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semc: semc@402f0000 {
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compatible = "fsl,imxrt-semc";
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reg = <0x402f0000 0x4000>;
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clocks = <&clks IMXRT1050_CLK_SEMC>;
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pinctrl-0 = <&pinctrl_semc>;
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pinctrl-names = "default";
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status = "okay";
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};
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};
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};
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&semc {
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u-boot,dm-spl;
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/*
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* Memory configuration from sdram datasheet IS42S16160J-6BLI
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*/
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fsl,sdram-mux = /bits/ 8 <MUX_A8_SDRAM_A8
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MUX_CSX0_SDRAM_CS1
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0
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0
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0
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0>;
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fsl,sdram-control = /bits/ 8 <MEM_WIDTH_16BITS
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BL_8
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COL_9BITS
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CL_3>;
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fsl,sdram-timing = /bits/ 8 <0x2
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0x2
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0x9
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0x1
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0x5
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0x6
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0x20
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0x09
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0x01
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0x00
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0x04
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0x0A
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0x21
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0x50>;
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bank1: bank@0 {
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fsl,base-address = <0x80000000>;
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fsl,memory-size = <MEM_SIZE_32M>;
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u-boot,dm-spl;
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2021-05-16 21:57:00 +00:00
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};
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};
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&osc {
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u-boot,dm-spl;
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};
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2022-03-17 18:33:18 +00:00
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&anatop {
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u-boot,dm-spl;
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};
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2021-05-16 21:57:00 +00:00
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&clks {
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u-boot,dm-spl;
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};
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&gpio1 {
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2022-11-07 21:22:36 +00:00
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compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
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2021-05-16 21:57:00 +00:00
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u-boot,dm-spl;
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};
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&gpio2 {
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2022-11-07 21:22:36 +00:00
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compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
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2021-05-16 21:57:00 +00:00
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u-boot,dm-spl;
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};
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&gpio3 {
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2022-11-07 21:22:36 +00:00
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compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
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2021-05-16 21:57:00 +00:00
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u-boot,dm-spl;
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};
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&gpio4 {
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2022-11-07 21:22:36 +00:00
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compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
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2021-05-16 21:57:00 +00:00
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u-boot,dm-spl;
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};
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&gpio5 {
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2022-11-07 21:22:36 +00:00
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compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
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2021-05-16 21:57:00 +00:00
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u-boot,dm-spl;
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2020-01-10 14:51:48 +00:00
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};
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2022-11-07 21:22:36 +00:00
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&gpt {
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clocks = <&osc>;
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compatible = "fsl,imxrt-gpt";
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status = "okay";
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2021-05-13 10:18:43 +00:00
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u-boot,dm-spl;
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};
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2020-01-10 14:51:48 +00:00
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&lpuart1 { /* console */
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2022-11-07 21:22:36 +00:00
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compatible = "fsl,imxrt-lpuart";
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clock-names = "per";
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2020-01-10 14:51:48 +00:00
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u-boot,dm-spl;
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};
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2022-11-07 21:22:36 +00:00
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&iomuxc {
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2021-05-16 21:57:00 +00:00
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u-boot,dm-spl;
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2022-11-07 21:22:36 +00:00
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compatible = "fsl,imxrt-iomuxc";
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pinctrl-0 = <&pinctrl_lpuart1>;
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2021-05-16 21:57:00 +00:00
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2022-11-07 21:22:36 +00:00
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pinctrl_semc: semcgrp {
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fsl,pins = <
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MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00
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0xf1 /* SEMC_D0 */
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MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01
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0xf1 /* SEMC_D1 */
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MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02
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0xf1 /* SEMC_D2 */
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MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03
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0xf1 /* SEMC_D3 */
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MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04
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0xf1 /* SEMC_D4 */
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MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05
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0xf1 /* SEMC_D5 */
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MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06
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0xf1 /* SEMC_D6 */
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MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07
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0xf1 /* SEMC_D7 */
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MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00
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0xf1 /* SEMC_DM0 */
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MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00
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0xf1 /* SEMC_A0 */
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MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01
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0xf1 /* SEMC_A1 */
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MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02
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0xf1 /* SEMC_A2 */
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MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03
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0xf1 /* SEMC_A3 */
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MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04
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0xf1 /* SEMC_A4 */
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MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05
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0xf1 /* SEMC_A5 */
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MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06
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0xf1 /* SEMC_A6 */
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MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07
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0xf1 /* SEMC_A7 */
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MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08
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0xf1 /* SEMC_A8 */
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MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09
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0xf1 /* SEMC_A9 */
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MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11
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0xf1 /* SEMC_A11 */
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MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12
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0xf1 /* SEMC_A12 */
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MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0
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0xf1 /* SEMC_BA0 */
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MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1
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0xf1 /* SEMC_BA1 */
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MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10
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0xf1 /* SEMC_A10 */
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MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS
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0xf1 /* SEMC_CAS */
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MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS
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0xf1 /* SEMC_RAS */
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MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK
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0xf1 /* SEMC_CLK */
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MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE
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0xf1 /* SEMC_CKE */
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MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE
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0xf1 /* SEMC_WE */
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MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0
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0xf1 /* SEMC_CS0 */
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MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08
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0xf1 /* SEMC_D8 */
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MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09
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0xf1 /* SEMC_D9 */
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MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10
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0xf1 /* SEMC_D10 */
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MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11
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0xf1 /* SEMC_D11 */
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MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12
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0xf1 /* SEMC_D12 */
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MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13
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0xf1 /* SEMC_D13 */
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MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14
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0xf1 /* SEMC_D14 */
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MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15
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0xf1 /* SEMC_D15 */
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MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01
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0xf1 /* SEMC_DM1 */
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MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS
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(IMX_PAD_SION | 0xf1) /* SEMC_DQS */
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>;
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2020-01-10 14:51:48 +00:00
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u-boot,dm-spl;
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};
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2022-11-07 21:22:36 +00:00
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pinctrl_lcdif: lcdifgrp {
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fsl,pins = <
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MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK 0x1b0b1
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MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE 0x1b0b1
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MXRT1050_IOMUXC_GPIO_B0_02_LCD_HSYNC 0x1b0b1
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MXRT1050_IOMUXC_GPIO_B0_03_LCD_VSYNC 0x1b0b1
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MXRT1050_IOMUXC_GPIO_B0_04_LCD_DATA00 0x1b0b1
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MXRT1050_IOMUXC_GPIO_B0_05_LCD_DATA01 0x1b0b1
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MXRT1050_IOMUXC_GPIO_B0_06_LCD_DATA02 0x1b0b1
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MXRT1050_IOMUXC_GPIO_B0_07_LCD_DATA03 0x1b0b1
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MXRT1050_IOMUXC_GPIO_B0_08_LCD_DATA04 0x1b0b1
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MXRT1050_IOMUXC_GPIO_B0_09_LCD_DATA05 0x1b0b1
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MXRT1050_IOMUXC_GPIO_B0_10_LCD_DATA06 0x1b0b1
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MXRT1050_IOMUXC_GPIO_B0_11_LCD_DATA07 0x1b0b1
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MXRT1050_IOMUXC_GPIO_B0_12_LCD_DATA08 0x1b0b1
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MXRT1050_IOMUXC_GPIO_B0_13_LCD_DATA09 0x1b0b1
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MXRT1050_IOMUXC_GPIO_B0_14_LCD_DATA10 0x1b0b1
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MXRT1050_IOMUXC_GPIO_B0_15_LCD_DATA11 0x1b0b1
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MXRT1050_IOMUXC_GPIO_B1_01_LCD_DATA13 0x1b0b1
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MXRT1050_IOMUXC_GPIO_B1_02_LCD_DATA14 0x1b0b1
|
|
|
|
|
MXRT1050_IOMUXC_GPIO_B1_03_LCD_DATA15 0x1b0b1
|
|
|
|
|
MXRT1050_IOMUXC_GPIO_B1_15_GPIO2_IO31 0x0b069
|
|
|
|
|
MXRT1050_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x0b069
|
|
|
|
|
>;
|
|
|
|
|
};
|
2020-01-10 14:51:48 +00:00
|
|
|
|
2022-11-07 21:22:36 +00:00
|
|
|
pinctrl_lpuart1: lpuart1grp {
|
2020-01-10 14:51:48 +00:00
|
|
|
u-boot,dm-spl;
|
2022-11-07 21:22:36 +00:00
|
|
|
};
|
2020-01-10 14:51:48 +00:00
|
|
|
|
2022-11-07 21:22:36 +00:00
|
|
|
pinctrl_usdhc0: usdhc0grp {
|
|
|
|
|
u-boot,dm-spl;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&usdhc1 {
|
|
|
|
|
compatible = "fsl,imxrt-usdhc";
|
|
|
|
|
u-boot,dm-spl;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&lcdif {
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&pinctrl_lcdif>;
|
|
|
|
|
display = <&display0>;
|
|
|
|
|
status = "okay";
|
|
|
|
|
|
|
|
|
|
display0: display0 {
|
|
|
|
|
bits-per-pixel = <16>;
|
|
|
|
|
bus-width = <16>;
|
2020-01-10 14:51:48 +00:00
|
|
|
|
2022-11-07 21:22:36 +00:00
|
|
|
display-timings {
|
|
|
|
|
timing0: timing0 {
|
|
|
|
|
clock-frequency = <9300000>;
|
|
|
|
|
hactive = <480>;
|
|
|
|
|
vactive = <272>;
|
|
|
|
|
hback-porch = <4>;
|
|
|
|
|
hfront-porch = <8>;
|
|
|
|
|
vback-porch = <4>;
|
|
|
|
|
vfront-porch = <8>;
|
|
|
|
|
hsync-len = <41>;
|
|
|
|
|
vsync-len = <10>;
|
|
|
|
|
de-active = <1>;
|
|
|
|
|
pixelclk-active = <0>;
|
|
|
|
|
hsync-active = <0>;
|
|
|
|
|
vsync-active = <0>;
|
|
|
|
|
};
|
2020-01-10 14:51:48 +00:00
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2022-11-07 21:22:36 +00:00
|
|
|
&usbotg1 {
|
|
|
|
|
dr_mode = "host";
|
|
|
|
|
status = "okay";
|
2020-01-10 14:51:48 +00:00
|
|
|
};
|
