2018-05-06 21:58:06 +00:00
|
|
|
// SPDX-License-Identifier: GPL-2.0+
|
2014-11-24 09:11:56 +00:00
|
|
|
/*
|
|
|
|
* Copyright 2014 Freescale Semiconductor, Inc.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include <common.h>
|
|
|
|
#include <asm/fsl_law.h>
|
|
|
|
#include <asm/mmu.h>
|
|
|
|
|
|
|
|
struct law_entry law_table[] = {
|
2017-02-11 13:43:54 +00:00
|
|
|
#ifdef CONFIG_MTD_NOR_FLASH
|
2022-11-16 18:10:41 +00:00
|
|
|
SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
|
2014-11-24 09:11:56 +00:00
|
|
|
#endif
|
2022-11-16 18:10:41 +00:00
|
|
|
#ifdef CFG_SYS_BMAN_MEM_PHYS
|
|
|
|
SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
|
2014-11-24 09:11:56 +00:00
|
|
|
#endif
|
2022-11-16 18:10:41 +00:00
|
|
|
#ifdef CFG_SYS_QMAN_MEM_PHYS
|
|
|
|
SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
|
2014-11-24 09:11:56 +00:00
|
|
|
#endif
|
2022-11-16 18:10:41 +00:00
|
|
|
#ifdef CFG_SYS_CPLD_BASE_PHYS
|
|
|
|
SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
|
2014-11-24 09:11:56 +00:00
|
|
|
#endif
|
2022-11-16 18:10:41 +00:00
|
|
|
#ifdef CFG_SYS_DCSRBAR_PHYS
|
|
|
|
SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
|
2014-11-24 09:11:56 +00:00
|
|
|
#endif
|
2022-11-12 22:36:51 +00:00
|
|
|
#ifdef CFG_SYS_NAND_BASE_PHYS
|
|
|
|
SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
|
2014-11-24 09:11:56 +00:00
|
|
|
#endif
|
|
|
|
};
|
|
|
|
|
|
|
|
int num_law_entries = ARRAY_SIZE(law_table);
|