u-boot/arch/arm/dts/socfpga_cyclone5_socrates.dts

/*
 *  Copyright (C) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include "socfpga_cyclone5.dtsi"

/ {
	model = "EBV SOCrates";
	compatible = "ebv,socrates", "altr,socfpga-cyclone5", "altr,socfpga";

	chosen {
		bootargs = "console=ttyS0,115200";
	};

 	aliases {
		spi0 = "/spi@ff705000";		/* QSPI */
		spi1 = "/spi@fff00000";
		spi2 = "/spi@fff01000";
 	};

	memory {
		name = "memory";
		device_type = "memory";
		reg = <0x0 0x40000000>; /* 1GB */
	};
};

&gmac1 {
	status = "okay";
};

&i2c0 {
	status = "okay";

	rtc: rtc@68 {
		compatible = "stm,m41t82";
		reg = <0x68>;
	};
};

&mmc {
	status = "okay";
};

&qspi {
	status = "okay";

	flash0: n25q00@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "n25q00";
		reg = <0>;      /* chip select */
		spi-max-frequency = <50000000>;
		m25p,fast-read;
		page-size = <256>;
		block-size = <16>; /* 2^16, 64KB */
		read-delay = <4>;  /* delay value in read data capture register */
		tshsl-ns = <50>;
		tsd2d-ns = <50>;
		tchsh-ns = <4>;
		tslch-ns = <4>;
	};
};
arm: socfpga: Add DT support for SoCFPGA and add socfpga_socrates target This patch includes the latest DT sources for socfpga from the current Linux kernel. And enables CONFIG_OF_CONTROL for the new build target "socfpga_socrates" (the EBV SoCrates board) to make use of this new DT support. Until this patch, the only SoCFPGA U-Boot target in mainline is "socfpga_cyclone5". This build target is not (yet) changed to support DT. So nothing changes for this target. Even though the long-term goal should be to move all SoCFPGA targets over to DT. One of the reasons to enable DT support in SoCFPGA is, that I need to support multiple different SPI controllers for this platform. This is the QSPI Cadence controller and the Designware SPI master controller. Both are implemented in the SoCFPGA. And enabling both controllers is only possible by using the new driver model (DM). The DM SPI code only supports DT based probing. So it was easier to move SoCFPGA to DT than to add the (deprecated) platform-data based probing to the DM SPI suport. Note that the image with the dtb embedded is u-boot-dtb.img. This needs to be used now for those DT enabled boards instead of u-boot.img. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Pavel Machek <pavel@denx.de> Cc: Simon Glass <sjg@chromium.org> 2014-11-07 13:10:41 +00:00			`/*`
			`* Copyright (C) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>`
			`*`
arm: socfpga: dts: Move to SPDX license identifiers The socfpga dts files are copied from the Rocketboards.org repository. In U-Boot we usually replace the full-blown license header text with the SPDX license identifiers. Lets do this for these new dts files as well. I just forgot to do this while adding the DT support for socfpga. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> 2014-11-14 07:10:44 +00:00			`* SPDX-License-Identifier: GPL-2.0+`
arm: socfpga: Add DT support for SoCFPGA and add socfpga_socrates target This patch includes the latest DT sources for socfpga from the current Linux kernel. And enables CONFIG_OF_CONTROL for the new build target "socfpga_socrates" (the EBV SoCrates board) to make use of this new DT support. Until this patch, the only SoCFPGA U-Boot target in mainline is "socfpga_cyclone5". This build target is not (yet) changed to support DT. So nothing changes for this target. Even though the long-term goal should be to move all SoCFPGA targets over to DT. One of the reasons to enable DT support in SoCFPGA is, that I need to support multiple different SPI controllers for this platform. This is the QSPI Cadence controller and the Designware SPI master controller. Both are implemented in the SoCFPGA. And enabling both controllers is only possible by using the new driver model (DM). The DM SPI code only supports DT based probing. So it was easier to move SoCFPGA to DT than to add the (deprecated) platform-data based probing to the DM SPI suport. Note that the image with the dtb embedded is u-boot-dtb.img. This needs to be used now for those DT enabled boards instead of u-boot.img. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Pavel Machek <pavel@denx.de> Cc: Simon Glass <sjg@chromium.org> 2014-11-07 13:10:41 +00:00			`*/`

			`#include "socfpga_cyclone5.dtsi"`

			`/ {`
			`model = "EBV SOCrates";`
			`compatible = "ebv,socrates", "altr,socfpga-cyclone5", "altr,socfpga";`

			`chosen {`
			`bootargs = "console=ttyS0,115200";`
			`};`

arm: socfpga: dts: Add spi0 alias for Cadence QSPI driver Without this alias, DM based probing does not work. So lets add this alias to get the bus numbering correct. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> 2014-11-07 11:37:51 +00:00			`aliases {`
			`spi0 = "/spi@ff705000"; /* QSPI */`
arm: socfpga: dts: socrates: Add spi1/2 aliases needed DM SPI probing Without this alias, DM based probing does not work. So lets add this alias to get the bus numbering correct for the Designware SPI controllers. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de> 2014-11-07 12:50:33 +00:00			`spi1 = "/spi@fff00000";`
			`spi2 = "/spi@fff01000";`
arm: socfpga: dts: Add spi0 alias for Cadence QSPI driver Without this alias, DM based probing does not work. So lets add this alias to get the bus numbering correct. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> 2014-11-07 11:37:51 +00:00			`};`

arm: socfpga: Add DT support for SoCFPGA and add socfpga_socrates target This patch includes the latest DT sources for socfpga from the current Linux kernel. And enables CONFIG_OF_CONTROL for the new build target "socfpga_socrates" (the EBV SoCrates board) to make use of this new DT support. Until this patch, the only SoCFPGA U-Boot target in mainline is "socfpga_cyclone5". This build target is not (yet) changed to support DT. So nothing changes for this target. Even though the long-term goal should be to move all SoCFPGA targets over to DT. One of the reasons to enable DT support in SoCFPGA is, that I need to support multiple different SPI controllers for this platform. This is the QSPI Cadence controller and the Designware SPI master controller. Both are implemented in the SoCFPGA. And enabling both controllers is only possible by using the new driver model (DM). The DM SPI code only supports DT based probing. So it was easier to move SoCFPGA to DT than to add the (deprecated) platform-data based probing to the DM SPI suport. Note that the image with the dtb embedded is u-boot-dtb.img. This needs to be used now for those DT enabled boards instead of u-boot.img. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Pavel Machek <pavel@denx.de> Cc: Simon Glass <sjg@chromium.org> 2014-11-07 13:10:41 +00:00			`memory {`
			`name = "memory";`
			`device_type = "memory";`
			`reg = <0x0 0x40000000>; /* 1GB */`
			`};`
			`};`

			`&gmac1 {`
			`status = "okay";`
			`};`

			`&i2c0 {`
			`status = "okay";`

			`rtc: rtc@68 {`
			`compatible = "stm,m41t82";`
			`reg = <0x68>;`
			`};`
			`};`

			`&mmc {`
			`status = "okay";`
			`};`
arm: socfpga: dts: Add Cadence QSPI DT node to socfpga.dtsi This DT node is taken from the Rocketboard.org Linux repsitory. And is needed to enable (configure) the Cadence DM SPI driver. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> 2014-11-07 11:37:50 +00:00
			`&qspi {`
			`status = "okay";`

			`flash0: n25q00@0 {`
			`#address-cells = <1>;`
			`#size-cells = <1>;`
			`compatible = "n25q00";`
			`reg = <0>; /* chip select */`
			`spi-max-frequency = <50000000>;`
			`m25p,fast-read;`
			`page-size = <256>;`
			`block-size = <16>; /* 2^16, 64KB */`
			`read-delay = <4>; /* delay value in read data capture register */`
			`tshsl-ns = <50>;`
			`tsd2d-ns = <50>;`
			`tchsh-ns = <4>;`
			`tslch-ns = <4>;`
			`};`
			`};`