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348 lines
11 KiB
C
348 lines
11 KiB
C
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/*
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* linux/include/asm-arm/arch-netarm/netarm_ser_module.h
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*
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* Copyright (C) 2000 NETsilicon, Inc.
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* Copyright (C) 2000 Red Hat, Inc.
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*
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* This software is copyrighted by Red Hat. LICENSEE agrees that
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* it will not delete this copyright notice, trademarks or protective
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* notices from any copy made by LICENSEE.
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*
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* This software is provided "AS-IS" and any express or implied
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* warranties or conditions, including but not limited to any
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* implied warranties of merchantability and fitness for a particular
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* purpose regarding this software. In no event shall Red Hat
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* be liable for any indirect, consequential, or incidental damages,
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* loss of profits or revenue, loss of use or data, or interruption
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* of business, whether the alleged damages are labeled in contract,
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* tort, or indemnity.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* author(s) : Joe deBlaquiere
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* Clark Williams
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*/
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#ifndef __NETARM_SER_MODULE_REGISTERS_H
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#define __NETARM_SER_MODULE_REGISTERS_H
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#ifndef __ASSEMBLER__
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/* (--sub)#include "types.h" */
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/* serial channel control structure */
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typedef struct {
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u32 ctrl_a;
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u32 ctrl_b;
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u32 status_a;
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u32 bitrate;
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u32 fifo;
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u32 rx_buf_timer;
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u32 rx_char_timer;
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u32 rx_match;
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u32 rx_match_mask;
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u32 ctrl_c;
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u32 status_b;
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u32 status_c;
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u32 fifo_last;
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u32 unused[3];
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} netarm_serial_channel_t;
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#endif
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/* SER unit register offsets */
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/* #ifdef CONFIG_ARCH_NETARM */
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#define NETARM_SER_MODULE_BASE (0xFFD00000)
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/* #else */
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/* extern serial_channel_t netarm_dummy_registers[]; */
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/* #define NETARM_SER_MODULE_BASE (netarm_dummy_registers) */
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/* #ifndef NETARM_XTAL_FREQ */
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/* #define NETARM_XTAL_FREQ 18432000 */
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/* #endif */
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/* #endif */
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/* calculate the sysclk value from the pll setting */
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#define NETARM_PLLED_SYSCLK_FREQ (( NETARM_XTAL_FREQ / 5 ) * \
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( NETARM_PLL_COUNT_VAL + 3 ))
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#define get_serial_channel(c) (&(((netarm_serial_channel_t *)NETARM_SER_MODULE_BASE)[c]))
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#define NETARM_SER_CH1_CTRL_A (0x00)
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#define NETARM_SER_CH1_CTRL_B (0x04)
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#define NETARM_SER_CH1_STATUS_A (0x08)
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#define NETARM_SER_CH1_BITRATE (0x0C)
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#define NETARM_SER_CH1_FIFO (0x10)
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#define NETARM_SER_CH1_RX_BUF_TMR (0x14)
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#define NETARM_SER_CH1_RX_CHAR_TMR (0x18)
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#define NETARM_SER_CH1_RX_MATCH (0x1c)
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#define NETARM_SER_CH1_RX_MATCH_MASK (0x20)
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#define NETARM_SER_CH1_CTRL_C (0x24)
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#define NETARM_SER_CH1_STATUS_B (0x28)
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#define NETARM_SER_CH1_STATUS_C (0x2c)
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#define NETARM_SER_CH1_FIFO_LAST (0x30)
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#define NETARM_SER_CH2_CTRL_A (0x40)
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#define NETARM_SER_CH2_CTRL_B (0x44)
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#define NETARM_SER_CH2_STATUS_A (0x48)
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#define NETARM_SER_CH2_BITRATE (0x4C)
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#define NETARM_SER_CH2_FIFO (0x50)
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#define NETARM_SER_CH2_RX_BUF_TMR (0x54)
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#define NETARM_SER_CH2_RX_CHAR_TMR (0x58)
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#define NETARM_SER_CH2_RX_MATCH (0x5c)
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#define NETARM_SER_CH2_RX_MATCH_MASK (0x60)
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#define NETARM_SER_CH2_CTRL_C (0x64)
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#define NETARM_SER_CH2_STATUS_B (0x68)
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#define NETARM_SER_CH2_STATUS_C (0x6c)
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#define NETARM_SER_CH2_FIFO_LAST (0x70)
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/* select bitfield defintions */
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/* Control Register A */
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#define NETARM_SER_CTLA_ENABLE (0x80000000)
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#define NETARM_SER_CTLA_BRK (0x40000000)
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#define NETARM_SER_CTLA_STICKP (0x20000000)
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#define NETARM_SER_CTLA_P_EVEN (0x18000000)
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#define NETARM_SER_CTLA_P_ODD (0x08000000)
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#define NETARM_SER_CTLA_P_NONE (0x00000000)
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/* if you read the errata, you will find that the STOP bits don't work right */
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#define NETARM_SER_CTLA_2STOP (0x00000000)
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#define NETARM_SER_CTLA_3STOP (0x04000000)
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#define NETARM_SER_CTLA_5BITS (0x00000000)
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#define NETARM_SER_CTLA_6BITS (0x01000000)
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#define NETARM_SER_CTLA_7BITS (0x02000000)
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#define NETARM_SER_CTLA_8BITS (0x03000000)
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#define NETARM_SER_CTLA_CTSTX (0x00800000)
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#define NETARM_SER_CTLA_RTSRX (0x00400000)
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#define NETARM_SER_CTLA_LOOP_REM (0x00200000)
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#define NETARM_SER_CTLA_LOOP_LOC (0x00100000)
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#define NETARM_SER_CTLA_GPIO2 (0x00080000)
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#define NETARM_SER_CTLA_GPIO1 (0x00040000)
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#define NETARM_SER_CTLA_DTR_EN (0x00020000)
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#define NETARM_SER_CTLA_RTS_EN (0x00010000)
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#define NETARM_SER_CTLA_IE_RX_BRK (0x00008000)
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#define NETARM_SER_CTLA_IE_RX_FRMERR (0x00004000)
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#define NETARM_SER_CTLA_IE_RX_PARERR (0x00002000)
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#define NETARM_SER_CTLA_IE_RX_OVERRUN (0x00001000)
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#define NETARM_SER_CTLA_IE_RX_RDY (0x00000800)
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#define NETARM_SER_CTLA_IE_RX_HALF (0x00000400)
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#define NETARM_SER_CTLA_IE_RX_FULL (0x00000200)
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#define NETARM_SER_CTLA_IE_RX_DMAEN (0x00000100)
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#define NETARM_SER_CTLA_IE_RX_DCD (0x00000080)
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#define NETARM_SER_CTLA_IE_RX_RI (0x00000040)
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#define NETARM_SER_CTLA_IE_RX_DSR (0x00000020)
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#define NETARM_SER_CTLA_IE_RX_ALL (NETARM_SER_CTLA_IE_RX_BRK \
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|NETARM_SER_CTLA_IE_RX_FRMERR \
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|NETARM_SER_CTLA_IE_RX_PARERR \
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|NETARM_SER_CTLA_IE_RX_OVERRUN \
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|NETARM_SER_CTLA_IE_RX_RDY \
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|NETARM_SER_CTLA_IE_RX_HALF \
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|NETARM_SER_CTLA_IE_RX_FULL \
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|NETARM_SER_CTLA_IE_RX_DMAEN \
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|NETARM_SER_CTLA_IE_RX_DCD \
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|NETARM_SER_CTLA_IE_RX_RI \
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|NETARM_SER_CTLA_IE_RX_DSR)
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#define NETARM_SER_CTLA_IE_TX_CTS (0x00000010)
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#define NETARM_SER_CTLA_IE_TX_EMPTY (0x00000008)
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#define NETARM_SER_CTLA_IE_TX_HALF (0x00000004)
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#define NETARM_SER_CTLA_IE_TX_FULL (0x00000002)
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#define NETARM_SER_CTLA_IE_TX_DMAEN (0x00000001)
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#define NETARM_SER_CTLA_IE_TX_ALL (NETARM_SER_CTLA_IE_TX_CTS \
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|NETARM_SER_CTLA_IE_TX_EMPTY \
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|NETARM_SER_CTLA_IE_TX_HALF \
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|NETARM_SER_CTLA_IE_TX_FULL \
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|NETARM_SER_CTLA_IE_TX_DMAEN)
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/* Control Register B */
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#define NETARM_SER_CTLB_MATCH1_EN (0x80000000)
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#define NETARM_SER_CTLB_MATCH2_EN (0x40000000)
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#define NETARM_SER_CTLB_MATCH3_EN (0x20000000)
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#define NETARM_SER_CTLB_MATCH4_EN (0x10000000)
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#define NETARM_SER_CTLB_RBGT_EN (0x08000000)
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#define NETARM_SER_CTLB_RCGT_EN (0x04000000)
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#define NETARM_SER_CTLB_UART_MODE (0x00000000)
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#define NETARM_SER_CTLB_HDLC_MODE (0x00100000)
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#define NETARM_SER_CTLB_SPI_MAS_MODE (0x00200000)
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#define NETARM_SER_CTLB_SPI_SLV_MODE (0x00300000)
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#define NETARM_SER_CTLB_REV_BIT_ORDER (0x00080000)
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#define NETARM_SER_CTLB_MAM1 (0x00040000)
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#define NETARM_SER_CTLB_MAM2 (0x00020000)
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/* Status Register A */
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#define NETARM_SER_STATA_MATCH1 (0x80000000)
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#define NETARM_SER_STATA_MATCH2 (0x40000000)
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#define NETARM_SER_STATA_MATCH3 (0x20000000)
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#define NETARM_SER_STATA_MATCH4 (0x10000000)
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#define NETARM_SER_STATA_BGAP (0x80000000)
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#define NETARM_SER_STATA_CGAP (0x40000000)
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#define NETARM_SER_STATA_RX_1B (0x00100000)
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#define NETARM_SER_STATA_RX_2B (0x00200000)
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#define NETARM_SER_STATA_RX_3B (0x00300000)
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#define NETARM_SER_STATA_RX_4B (0x00000000)
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/* downshifted values */
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#define NETARM_SER_STATA_RXFDB_1BYTES (0x001)
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#define NETARM_SER_STATA_RXFDB_2BYTES (0x002)
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#define NETARM_SER_STATA_RXFDB_3BYTES (0x003)
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#define NETARM_SER_STATA_RXFDB_4BYTES (0x000)
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#define NETARM_SER_STATA_RXFDB_MASK (0x00300000)
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#define NETARM_SER_STATA_RXFDB(x) (((x) & NETARM_SER_STATA_RXFDB_MASK) \
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>> 20)
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#define NETARM_SER_STATA_DCD (0x00080000)
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#define NETARM_SER_STATA_RI (0x00040000)
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#define NETARM_SER_STATA_DSR (0x00020000)
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#define NETARM_SER_STATA_CTS (0x00010000)
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#define NETARM_SER_STATA_RX_BRK (0x00008000)
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#define NETARM_SER_STATA_RX_FRMERR (0x00004000)
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#define NETARM_SER_STATA_RX_PARERR (0x00002000)
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#define NETARM_SER_STATA_RX_OVERRUN (0x00001000)
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#define NETARM_SER_STATA_RX_RDY (0x00000800)
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#define NETARM_SER_STATA_RX_HALF (0x00000400)
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#define NETARM_SER_STATA_RX_CLOSED (0x00000200)
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#define NETARM_SER_STATA_RX_FULL (0x00000100)
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#define NETARM_SER_STATA_RX_DCD (0x00000080)
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#define NETARM_SER_STATA_RX_RI (0x00000040)
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#define NETARM_SER_STATA_RX_DSR (0x00000020)
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#define NETARM_SER_STATA_TX_CTS (0x00000010)
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#define NETARM_SER_STATA_TX_RDY (0x00000008)
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#define NETARM_SER_STATA_TX_HALF (0x00000004)
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#define NETARM_SER_STATA_TX_FULL (0x00000002)
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#define NETARM_SER_STATA_TX_DMAEN (0x00000001)
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/* you have to clear all receive signals to get the fifo to move forward */
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#define NETARM_SER_STATA_CLR_ALL (NETARM_SER_STATA_RX_BRK | \
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NETARM_SER_STATA_RX_FRMERR | \
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NETARM_SER_STATA_RX_PARERR | \
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NETARM_SER_STATA_RX_OVERRUN | \
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NETARM_SER_STATA_RX_HALF | \
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NETARM_SER_STATA_RX_CLOSED | \
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NETARM_SER_STATA_RX_FULL | \
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NETARM_SER_STATA_RX_DCD | \
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NETARM_SER_STATA_RX_RI | \
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NETARM_SER_STATA_RX_DSR | \
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NETARM_SER_STATA_TX_CTS )
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/* Bit Rate Registers */
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#define NETARM_SER_BR_EN (0x80000000)
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#define NETARM_SER_BR_TMODE (0x40000000)
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#define NETARM_SER_BR_RX_CLK_INT (0x00000000)
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#define NETARM_SER_BR_RX_CLK_EXT (0x20000000)
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#define NETARM_SER_BR_TX_CLK_INT (0x00000000)
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#define NETARM_SER_BR_TX_CLK_EXT (0x10000000)
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#define NETARM_SER_BR_RX_CLK_DRV (0x08000000)
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#define NETARM_SER_BR_TX_CLK_DRV (0x04000000)
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#define NETARM_SER_BR_CLK_EXT_5 (0x00000000)
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#define NETARM_SER_BR_CLK_SYSTEM (0x01000000)
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#define NETARM_SER_BR_CLK_OUT1A (0x02000000)
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#define NETARM_SER_BR_CLK_OUT2A (0x03000000)
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#define NETARM_SER_BR_TX_CLK_INV (0x00800000)
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#define NETARM_SER_BR_RX_CLK_INV (0x00400000)
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/* complete settings assuming system clock input is 18MHz */
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#define NETARM_SER_BR_MASK (0x000007FF)
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/* bit rate determined from equation Fbr = Fxtal / [ 10 * ( N + 1 ) ] */
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/* from section 7.5.4 of HW Ref Guide */
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/* #ifdef CONFIG_NETARM_PLL_BYPASS */
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#define NETARM_SER_BR_X16(x) ( NETARM_SER_BR_EN | \
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NETARM_SER_BR_RX_CLK_INT | \
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NETARM_SER_BR_TX_CLK_INT | \
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NETARM_SER_BR_CLK_EXT_5 | \
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( ( ( ( NETARM_XTAL_FREQ / \
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( x * 10 ) ) - 1 ) / 16 ) & \
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NETARM_SER_BR_MASK ) )
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/*
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#else
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#define NETARM_SER_BR_X16(x) ( NETARM_SER_BR_EN | \
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NETARM_SER_BR_RX_CLK_INT | \
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NETARM_SER_BR_TX_CLK_INT | \
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NETARM_SER_BR_CLK_SYSTEM | \
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||
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( ( ( ( NETARM_PLLED_SYSCLK_FREQ / \
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||
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( x * 2 ) ) - 1 ) / 16 ) & \
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||
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NETARM_SER_BR_MASK ) )
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||
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#endif
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||
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*/
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||
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||
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/* Receive Buffer Gap Timer */
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||
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|
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||
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#define NETARM_SER_RX_GAP_TIMER_EN (0x80000000)
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||
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#define NETARM_SER_RX_GAP_MASK (0x00003FFF)
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||
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|
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||
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/* rx gap is a function of bit rate x */
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||
|
|
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||
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/* #ifdef CONFIG_NETARM_PLL_BYPASS */
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||
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#define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \
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||
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|
( ( ( ( 10 * NETARM_XTAL_FREQ ) / \
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||
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|
( x * 5 * 512 ) ) - 1 ) & \
|
||
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|
NETARM_SER_RX_GAP_MASK ) )
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||
|
|
/*
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||
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|
#else
|
||
|
|
#define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \
|
||
|
|
( ( ( ( 2 * NETARM_PLLED_SYSCLK_FREQ ) / \
|
||
|
|
( x * 512 ) ) - 1 ) & \
|
||
|
|
NETARM_SER_RX_GAP_MASK ) )
|
||
|
|
#endif
|
||
|
|
*/
|
||
|
|
|
||
|
|
#if 0
|
||
|
|
#define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \
|
||
|
|
( ( ( ( 2 * NETARM_PLLED_SYSCLK_FREQ ) / \
|
||
|
|
( x * 5 * 512 ) ) - 1 ) & \
|
||
|
|
NETARM_SER_RX_GAP_MASK ) )
|
||
|
|
#define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \
|
||
|
|
( ( ( ( 10 * NETARM_XTAL_FREQ ) / \
|
||
|
|
( x * 512 ) ) - 1 ) & \
|
||
|
|
NETARM_SER_RX_GAP_MASK ) )
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#define MIN_BAUD_RATE 600
|
||
|
|
#define MAX_BAUD_RATE 115200
|
||
|
|
|
||
|
|
/* the default BAUD rate for the BOOTLOADER, there is a separate */
|
||
|
|
/* setting in the serial driver <arch/armnommu/drivers/char/serial-netarm.h> */
|
||
|
|
#define DEFAULT_BAUD_RATE 9600
|
||
|
|
#define NETARM_SER_FIFO_SIZE 32
|
||
|
|
#define MIN_GAP 0
|
||
|
|
|
||
|
|
#endif
|