2021-04-21 20:50:31 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2017 NXP
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* Copyright 2020 Linaro
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*
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*/
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#ifndef __COMPULAB_DDR_H__
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#define __COMPULAB_DDR_H__
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extern struct dram_timing_info ucm_dram_timing_ff020008;
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extern struct dram_timing_info ucm_dram_timing_ff000110;
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extern struct dram_timing_info ucm_dram_timing_01061010;
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void spl_dram_init_compulab(void);
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#define TCM_DATA_CFG 0x7e0000
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struct lpddr4_tcm_desc {
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unsigned int size;
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unsigned int sign;
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unsigned int index;
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unsigned int count;
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};
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2022-04-12 16:05:36 +00:00
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u32 cl_eeprom_get_ddrinfo(void);
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u32 cl_eeprom_set_ddrinfo(u32 ddrinfo);
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2023-03-13 18:26:20 +00:00
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u8 cl_eeprom_get_subind(void);
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u8 cl_eeprom_set_subind(u8 subind);
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2022-04-12 16:05:36 +00:00
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u32 cl_eeprom_get_osize(void);
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2021-04-21 20:50:31 +00:00
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#endif
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