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u-boot/arch/arm/include/asm/arch-stih410/sdhci.h

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SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-06 21:58:06 +00:00
/* SPDX-License-Identifier: GPL-2.0+ */
STiH410: Add STi SDHCI driver Add SDHCI host controller found on STMicroelectronics SoCs On some ST SoCs, i.e. STiH407/STiH410, the MMC devices can live inside a dedicated flashSS sub-system that provides an extend subset of registers that can be used to configure the Arasan MMC/SD Host Controller. This means, that the SDHCI Arasan Controller can be configured to be eMMC4.5 or 4.3 spec compliant. W/o these settings the SDHCI will configure and use the MMC/SD controller with limited features e.g. PIO mode, no DMA, no HS etc. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2017-02-21 12:37:09 +00:00
/*
sti: fix STMicroelectronics copyright Uniformize all STMicroelectronics copyrights headers for STi related code. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-10-23 07:53:57 +00:00
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
treewide: Update email address Patrick Delaunay and Patrice Chotard Update Patrick and my email address with the one dedicated to upstream activities. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-12-02 17:47:30 +00:00
* Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
STiH410: Add STi SDHCI driver Add SDHCI host controller found on STMicroelectronics SoCs On some ST SoCs, i.e. STiH407/STiH410, the MMC devices can live inside a dedicated flashSS sub-system that provides an extend subset of registers that can be used to configure the Arasan MMC/SD Host Controller. This means, that the SDHCI Arasan Controller can be configured to be eMMC4.5 or 4.3 spec compliant. W/o these settings the SDHCI will configure and use the MMC/SD controller with limited features e.g. PIO mode, no DMA, no HS etc. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2017-02-21 12:37:09 +00:00
*/
#ifndef __STI_SDHCI_H__
#define __STI_SDHCI_H__
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-10 17:40:13 +00:00
#ifndef __ASSEMBLY__
#include <linux/bitops.h>
#endif
STiH410: Add STi SDHCI driver Add SDHCI host controller found on STMicroelectronics SoCs On some ST SoCs, i.e. STiH407/STiH410, the MMC devices can live inside a dedicated flashSS sub-system that provides an extend subset of registers that can be used to configure the Arasan MMC/SD Host Controller. This means, that the SDHCI Arasan Controller can be configured to be eMMC4.5 or 4.3 spec compliant. W/o these settings the SDHCI will configure and use the MMC/SD controller with limited features e.g. PIO mode, no DMA, no HS etc. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2017-02-21 12:37:09 +00:00
#define FLASHSS_MMC_CORE_CONFIG_1 0x400
#define FLASHSS_MMC_CORECFG_TIMEOUT_CLK_UNIT_MHZ BIT(24)
#define FLASHSS_MMC_CORECFG_TIMEOUT_CLK_FREQ_MIN BIT(12)
#define STI_FLASHSS_MMC_CORE_CONFIG_1 \
(FLASHSS_MMC_CORECFG_TIMEOUT_CLK_UNIT_MHZ | \
FLASHSS_MMC_CORECFG_TIMEOUT_CLK_FREQ_MIN)
#define FLASHSS_MMC_CORE_CONFIG_2 0x404
#define FLASHSS_MMC_CORECFG_HIGH_SPEED BIT(28)
#define FLASHSS_MMC_CORECFG_8BIT_EMMC BIT(20)
#define MAX_BLK_LENGTH_1024 BIT(16)
#define BASE_CLK_FREQ_200 0xc8
#define STI_FLASHSS_MMC_CORE_CONFIG2 \
(FLASHSS_MMC_CORECFG_HIGH_SPEED | \
FLASHSS_MMC_CORECFG_8BIT_EMMC | \
MAX_BLK_LENGTH_1024 | \
BASE_CLK_FREQ_200 << 0)
#define STI_FLASHSS_SDCARD_CORE_CONFIG2 \
(FLASHSS_MMC_CORECFG_HIGH_SPEED | \
MAX_BLK_LENGTH_1024 | \
BASE_CLK_FREQ_200)
#define FLASHSS_MMC_CORE_CONFIG_3 0x408
#define FLASHSS_MMC_CORECFG_SLOT_TYPE_EMMC BIT(28)
#define FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT BIT(20)
#define FLASHSS_MMC_CORECFG_3P3_VOLT BIT(8)
#define FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT BIT(4)
#define FLASHSS_MMC_CORECFG_SDMA BIT(0)
#define STI_FLASHSS_MMC_CORE_CONFIG3 \
(FLASHSS_MMC_CORECFG_SLOT_TYPE_EMMC | \
FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT | \
FLASHSS_MMC_CORECFG_3P3_VOLT | \
FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT | \
FLASHSS_MMC_CORECFG_SDMA)
#define STI_FLASHSS_SDCARD_CORE_CONFIG3 \
(FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT | \
FLASHSS_MMC_CORECFG_3P3_VOLT | \
FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT | \
FLASHSS_MMC_CORECFG_SDMA)
#define FLASHSS_MMC_CORE_CONFIG_4 0x40c
#define FLASHSS_MMC_CORECFG_D_DRIVER_SUPPORT BIT(20)
#define FLASHSS_MMC_CORECFG_C_DRIVER_SUPPORT BIT(16)
#define FLASHSS_MMC_CORECFG_A_DRIVER_SUPPORT BIT(12)
#define STI_FLASHSS_MMC_CORE_CONFIG4 \
(FLASHSS_MMC_CORECFG_D_DRIVER_SUPPORT | \
FLASHSS_MMC_CORECFG_C_DRIVER_SUPPORT | \
FLASHSS_MMC_CORECFG_A_DRIVER_SUPPORT)
#define ST_MMC_CCONFIG_REG_5 0x210
#define SYSCONF_MMC1_ENABLE_BIT 3
#endif /* _STI_SDHCI_H_ */
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