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u-boot/drivers/net/phy/marvell.c

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SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-06 21:58:06 +00:00
// SPDX-License-Identifier: GPL-2.0+
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-08 02:56:05 +00:00
/*
* Marvell PHY drivers
*
* Copyright 2010-2011 Freescale Semiconductor, Inc.
* author Andy Fleming
*/
#include <common.h>
net: phy: marvell: Add a missing errno.h header This corrects a build error on zynqmp. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-07-05 23:10:12 +00:00
#include <errno.h>
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-08 02:56:05 +00:00
#include <phy.h>
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-10 17:40:13 +00:00
#include <linux/bitops.h>
common: Drop linux/delay.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-10 17:40:11 +00:00
#include <linux/delay.h>
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-08 02:56:05 +00:00
#define PHY_AUTONEGOTIATE_TIMEOUT 5000
net: phy: marvell 88e151x: Fix handling of RGMII interface types The 88E1518 code is programming the wrong registers for rgmii-id, rgmii-txid and rgmii-rxid interfaces. Since the PHY defaults to rgmii-id, it would appear that the code was previously only used with sgmii and rgmii-id interfaces. Tested on 88E1512 PHY in rgmii-id mode which is from the same family as 88E1518. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-05-24 13:43:06 +00:00
#define MII_MARVELL_PHY_PAGE 22
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-08 02:56:05 +00:00
/* 88E1011 PHY Status Register */
#define MIIM_88E1xxx_PHY_STATUS 0x11
#define MIIM_88E1xxx_PHYSTAT_SPEED 0xc000
#define MIIM_88E1xxx_PHYSTAT_GBIT 0x8000
#define MIIM_88E1xxx_PHYSTAT_100 0x4000
#define MIIM_88E1xxx_PHYSTAT_DUPLEX 0x2000
#define MIIM_88E1xxx_PHYSTAT_SPDDONE 0x0800
#define MIIM_88E1xxx_PHYSTAT_LINK 0x0400
#define MIIM_88E1xxx_PHY_SCR 0x10
#define MIIM_88E1xxx_PHY_MDI_X_AUTO 0x0060
/* 88E1111 PHY LED Control Register */
#define MIIM_88E1111_PHY_LED_CONTROL 24
#define MIIM_88E1111_PHY_LED_DIRECT 0x4100
#define MIIM_88E1111_PHY_LED_COMBINE 0x411C
Phy/Marvell: Rewrite the MV88E1111 phy config function based on kernel code The original m88e1111s_config() does not do the SGMII mode initialization and is buggy. Rewrite the function according to 3.0.6 kernel function m88e1111_config_init() in drivers/net/phy/marvell.c Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com> Cc: Kumar Gala <galak@kernel.crashing.org>
2011-10-27 18:52:09 +00:00
/* 88E1111 Extended PHY Specific Control Register */
#define MIIM_88E1111_PHY_EXT_CR 0x14
#define MIIM_88E1111_RX_DELAY 0x80
#define MIIM_88E1111_TX_DELAY 0x2
/* 88E1111 Extended PHY Specific Status Register */
#define MIIM_88E1111_PHY_EXT_SR 0x1b
#define MIIM_88E1111_HWCFG_MODE_MASK 0xf
#define MIIM_88E1111_HWCFG_MODE_COPPER_RGMII 0xb
#define MIIM_88E1111_HWCFG_MODE_FIBER_RGMII 0x3
#define MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK 0x4
#define MIIM_88E1111_HWCFG_MODE_COPPER_RTBI 0x9
#define MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO 0x8000
#define MIIM_88E1111_HWCFG_FIBER_COPPER_RES 0x2000
#define MIIM_88E1111_COPPER 0
#define MIIM_88E1111_FIBER 1
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-08 02:56:05 +00:00
/* 88E1118 PHY defines */
#define MIIM_88E1118_PHY_PAGE 22
#define MIIM_88E1118_PHY_LED_PAGE 3
/* 88E1121 PHY LED Control Register */
#define MIIM_88E1121_PHY_LED_CTRL 16
#define MIIM_88E1121_PHY_LED_PAGE 3
#define MIIM_88E1121_PHY_LED_DEF 0x0030
/* 88E1121 PHY IRQ Enable/Status Register */
#define MIIM_88E1121_PHY_IRQ_EN 18
#define MIIM_88E1121_PHY_IRQ_STATUS 19
#define MIIM_88E1121_PHY_PAGE 22
/* 88E1145 Extended PHY Specific Control Register */
#define MIIM_88E1145_PHY_EXT_CR 20
#define MIIM_M88E1145_RGMII_RX_DELAY 0x0080
#define MIIM_M88E1145_RGMII_TX_DELAY 0x0002
#define MIIM_88E1145_PHY_LED_CONTROL 24
#define MIIM_88E1145_PHY_LED_DIRECT 0x4100
#define MIIM_88E1145_PHY_PAGE 29
#define MIIM_88E1145_PHY_CAL_OV 30
#define MIIM_88E1149_PHY_PAGE 29
NET: phy: add 88E1310 PHY initialization This adds PHY initialization for Marvell Alaska 88E1310 PHY. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2012-12-04 08:31:59 +00:00
/* 88E1310 PHY defines */
#define MIIM_88E1310_PHY_LED_CTRL 16
#define MIIM_88E1310_PHY_IRQ_EN 18
#define MIIM_88E1310_PHY_RGMII_CTRL 21
#define MIIM_88E1310_PHY_PAGE 22
net: phy: Improve the Marvell 151x constants Use some constants for the phy configuration instead of so many magic numbers. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2016-12-09 17:54:39 +00:00
/* 88E151x PHY defines */
net: phy: marvell 88e151x: Fix handling of RGMII interface types The 88E1518 code is programming the wrong registers for rgmii-id, rgmii-txid and rgmii-rxid interfaces. Since the PHY defaults to rgmii-id, it would appear that the code was previously only used with sgmii and rgmii-id interfaces. Tested on 88E1512 PHY in rgmii-id mode which is from the same family as 88E1518. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-05-24 13:43:06 +00:00
/* Page 2 registers */
#define MIIM_88E151x_PHY_MSCR 21
#define MIIM_88E151x_RGMII_RX_DELAY BIT(5)
#define MIIM_88E151x_RGMII_TX_DELAY BIT(4)
#define MIIM_88E151x_RGMII_RXTX_DELAY (BIT(5) | BIT(4))
net: phy: Improve the Marvell 151x constants Use some constants for the phy configuration instead of so many magic numbers. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2016-12-09 17:54:39 +00:00
/* Page 3 registers */
#define MIIM_88E151x_LED_FUNC_CTRL 16
#define MIIM_88E151x_LED_FLD_SZ 4
#define MIIM_88E151x_LED0_OFFS (0 * MIIM_88E151x_LED_FLD_SZ)
#define MIIM_88E151x_LED1_OFFS (1 * MIIM_88E151x_LED_FLD_SZ)
#define MIIM_88E151x_LED0_ACT 3
#define MIIM_88E151x_LED1_100_1000_LINK 6
#define MIIM_88E151x_LED_TIMER_CTRL 18
#define MIIM_88E151x_INT_EN_OFFS 7
/* Page 18 registers */
#define MIIM_88E151x_GENERAL_CTRL 20
#define MIIM_88E151x_MODE_SGMII 1
#define MIIM_88E151x_RESET_OFFS 15
net: phy: marvell: Support reg config via "marvell, reg-init" DT property This patch adds support for the "marvell,reg-init" DT property, which is used to describe board specific Marvell PHY register configurations in the board dts file. This DT property is supported in the Linux Kernel since a longer time. Adding it to U-Boot now, enables the boards which describe the register settings in their DT files here as well. I've included calling this marvell_of_reg_init() to all foo_config() functions in this patch as well. If CONFIG_DM_ETH is not set, there is no ofnode, or no "marvell,reg-init" property, the PHY initialization is unchanged. The function marvell_of_reg_init() is a port of the Linux version. Please note that I explicitly did not add error checking and handling to the U-Boot version, as this is basically not done for phy_read/write in this Marvell PHY code. This will be used by the upcoming ethernet support on the MIPS Octeon EBB 7304 board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Marek Behún <marek.behun@nic.cz> Reviewed-by: Marek Behún <marek.behun@nic.cz>
2022-03-31 09:43:06 +00:00
static int marvell_read_page(struct phy_device *phydev)
{
return phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE);
}
static int marvell_write_page(struct phy_device *phydev, int page)
{
return phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, page);
}
/* Set and/or override some configuration registers based on the
* marvell,reg-init property stored in the of_node for the phydev.
*
* marvell,reg-init = <reg-page reg mask value>,...;
*
* There may be one or more sets of <reg-page reg mask value>:
*
* reg-page: which register bank to use.
* reg: the register.
* mask: if non-zero, ANDed with existing register value.
* value: ORed with the masked value and written to the regiser.
*
*/
static int marvell_of_reg_init(struct phy_device *phydev)
{
const __be32 *prop;
int len, i, saved_page, current_page, ret = 0;
if (!ofnode_valid(phydev->node))
return 0;
prop = ofnode_get_property(phydev->node, "marvell,reg-init", &len);
if (!prop)
return 0;
saved_page = marvell_read_page(phydev);
if (saved_page < 0)
goto err;
current_page = saved_page;
len /= sizeof(*prop);
for (i = 0; i < len - 3; i += 4) {
u16 page = be32_to_cpup(prop + i);
u16 reg = be32_to_cpup(prop + i + 1);
u16 mask = be32_to_cpup(prop + i + 2);
u16 val_bits = be32_to_cpup(prop + i + 3);
int val;
if (page != current_page) {
current_page = page;
ret = marvell_write_page(phydev, page);
if (ret < 0)
goto err;
}
val = 0;
if (mask) {
val = phy_read(phydev, MDIO_DEVAD_NONE, reg);
if (val < 0) {
ret = val;
goto err;
}
val &= mask;
}
val |= val_bits;
ret = phy_write(phydev, MDIO_DEVAD_NONE, reg, val);
if (ret < 0)
goto err;
}
err:
return marvell_write_page(phydev, saved_page);
}
net: phy: marvell: Add functions to read PHY's extended registers This commit allows extended Marvell registers to be read with: foo > mdio rx FEC 3.10 Reading from bus FEC PHY at address 0: 3.16 - 0x1063 foo > mdio wx FEC 3.10 0x1011 The above code changes the way ETH connector LEDs blink. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: York Sun <york.sun@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-10-30 21:57:53 +00:00
static int m88e1xxx_phy_extread(struct phy_device *phydev, int addr,
int devaddr, int regnum)
{
int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE);
int val;
phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, devaddr);
val = phy_read(phydev, MDIO_DEVAD_NONE, regnum);
phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, oldpage);
return val;
}
static int m88e1xxx_phy_extwrite(struct phy_device *phydev, int addr,
int devaddr, int regnum, u16 val)
{
int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE);
phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, devaddr);
phy_write(phydev, MDIO_DEVAD_NONE, regnum, val);
phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, oldpage);
return 0;
}
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-08 02:56:05 +00:00
/* Marvell 88E1011S */
static int m88e1011s_config(struct phy_device *phydev)
{
/* Reset and configure the PHY */
phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
net: phy: marvell: Support reg config via "marvell, reg-init" DT property This patch adds support for the "marvell,reg-init" DT property, which is used to describe board specific Marvell PHY register configurations in the board dts file. This DT property is supported in the Linux Kernel since a longer time. Adding it to U-Boot now, enables the boards which describe the register settings in their DT files here as well. I've included calling this marvell_of_reg_init() to all foo_config() functions in this patch as well. If CONFIG_DM_ETH is not set, there is no ofnode, or no "marvell,reg-init" property, the PHY initialization is unchanged. The function marvell_of_reg_init() is a port of the Linux version. Please note that I explicitly did not add error checking and handling to the U-Boot version, as this is basically not done for phy_read/write in this Marvell PHY code. This will be used by the upcoming ethernet support on the MIPS Octeon EBB 7304 board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Marek Behún <marek.behun@nic.cz> Reviewed-by: Marek Behún <marek.behun@nic.cz>
2022-03-31 09:43:06 +00:00
marvell_of_reg_init(phydev);
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-08 02:56:05 +00:00
genphy_config_aneg(phydev);
return 0;
}
/* Parse the 88E1011's status register for speed and duplex
* information
*/
phy: Return correct error code when timeout happens Return -ETIMEDOUT if timeout happens. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Stephen Warren <swarren@nvidia.com>
2016-05-18 10:48:57 +00:00
static int m88e1xxx_parse_status(struct phy_device *phydev)
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-08 02:56:05 +00:00
{
unsigned int speed;
unsigned int mii_reg;
mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_STATUS);
if ((mii_reg & MIIM_88E1xxx_PHYSTAT_LINK) &&
net: phy: marvell: Fix style violations Fix some style violations (mostly wrong indentions) in the Marvell PHY driver. Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-15 10:08:24 +00:00
!(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) {
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-08 02:56:05 +00:00
int i = 0;
puts("Waiting for PHY realtime link");
while (!(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) {
/* Timeout reached ? */
if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
puts(" TIMEOUT !\n");
phydev->link = 0;
phy: Return correct error code when timeout happens Return -ETIMEDOUT if timeout happens. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Stephen Warren <swarren@nvidia.com>
2016-05-18 10:48:57 +00:00
return -ETIMEDOUT;
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-08 02:56:05 +00:00
}
if ((i++ % 1000) == 0)
putc('.');
udelay(1000);
mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
net: phy: marvell: Fix style violations Fix some style violations (mostly wrong indentions) in the Marvell PHY driver. Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-15 10:08:24 +00:00
MIIM_88E1xxx_PHY_STATUS);
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-08 02:56:05 +00:00
}
puts(" done\n");
net: phy: marvell: Fix style violations Fix some style violations (mostly wrong indentions) in the Marvell PHY driver. Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-15 10:08:24 +00:00
mdelay(500); /* another 500 ms (results in faster booting) */
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-08 02:56:05 +00:00
} else {
if (mii_reg & MIIM_88E1xxx_PHYSTAT_LINK)
phydev->link = 1;
else
phydev->link = 0;
}
if (mii_reg & MIIM_88E1xxx_PHYSTAT_DUPLEX)
phydev->duplex = DUPLEX_FULL;
else
phydev->duplex = DUPLEX_HALF;
speed = mii_reg & MIIM_88E1xxx_PHYSTAT_SPEED;
switch (speed) {
case MIIM_88E1xxx_PHYSTAT_GBIT:
phydev->speed = SPEED_1000;
break;
case MIIM_88E1xxx_PHYSTAT_100:
phydev->speed = SPEED_100;
break;
default:
phydev->speed = SPEED_10;
break;
}
return 0;
}
static int m88e1011s_startup(struct phy_device *phydev)
{
net: phy: Handle phy_startup() error codes properly Propagate error code from genphy_update_link() to phy startup(). Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Stephen Warren <swarren@nvidia.com>
2016-05-18 10:46:12 +00:00
int ret;
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-08 02:56:05 +00:00
net: phy: Handle phy_startup() error codes properly Propagate error code from genphy_update_link() to phy startup(). Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Stephen Warren <swarren@nvidia.com>
2016-05-18 10:46:12 +00:00
ret = genphy_update_link(phydev);
if (ret)
return ret;
return m88e1xxx_parse_status(phydev);
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-08 02:56:05 +00:00
}
/* Marvell 88E1111S */
static int m88e1111s_config(struct phy_device *phydev)
{
int reg;
net: phy: Marvell: Use phy_interface_is_rgmii helper function Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-12-12 12:54:15 +00:00
if (phy_interface_is_rgmii(phydev)) {
Phy/Marvell: Rewrite the MV88E1111 phy config function based on kernel code The original m88e1111s_config() does not do the SGMII mode initialization and is buggy. Rewrite the function according to 3.0.6 kernel function m88e1111_config_init() in drivers/net/phy/marvell.c Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com> Cc: Kumar Gala <galak@kernel.crashing.org>
2011-10-27 18:52:09 +00:00
reg = phy_read(phydev,
net: phy: marvell: Fix style violations Fix some style violations (mostly wrong indentions) in the Marvell PHY driver. Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-15 10:08:24 +00:00
MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR);
Phy/Marvell: Rewrite the MV88E1111 phy config function based on kernel code The original m88e1111s_config() does not do the SGMII mode initialization and is buggy. Rewrite the function according to 3.0.6 kernel function m88e1111_config_init() in drivers/net/phy/marvell.c Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com> Cc: Kumar Gala <galak@kernel.crashing.org>
2011-10-27 18:52:09 +00:00
if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
net: phy: marvell: Fix style violations Fix some style violations (mostly wrong indentions) in the Marvell PHY driver. Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-15 10:08:24 +00:00
(phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)) {
Phy/Marvell: Rewrite the MV88E1111 phy config function based on kernel code The original m88e1111s_config() does not do the SGMII mode initialization and is buggy. Rewrite the function according to 3.0.6 kernel function m88e1111_config_init() in drivers/net/phy/marvell.c Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com> Cc: Kumar Gala <galak@kernel.crashing.org>
2011-10-27 18:52:09 +00:00
reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY);
} else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
reg &= ~MIIM_88E1111_TX_DELAY;
reg |= MIIM_88E1111_RX_DELAY;
} else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
reg &= ~MIIM_88E1111_RX_DELAY;
reg |= MIIM_88E1111_TX_DELAY;
}
phy_write(phydev,
net: phy: marvell: Fix style violations Fix some style violations (mostly wrong indentions) in the Marvell PHY driver. Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-15 10:08:24 +00:00
MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg);
Phy/Marvell: Rewrite the MV88E1111 phy config function based on kernel code The original m88e1111s_config() does not do the SGMII mode initialization and is buggy. Rewrite the function according to 3.0.6 kernel function m88e1111_config_init() in drivers/net/phy/marvell.c Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com> Cc: Kumar Gala <galak@kernel.crashing.org>
2011-10-27 18:52:09 +00:00
reg = phy_read(phydev,
net: phy: marvell: Fix style violations Fix some style violations (mostly wrong indentions) in the Marvell PHY driver. Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-15 10:08:24 +00:00
MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR);
Phy/Marvell: Rewrite the MV88E1111 phy config function based on kernel code The original m88e1111s_config() does not do the SGMII mode initialization and is buggy. Rewrite the function according to 3.0.6 kernel function m88e1111_config_init() in drivers/net/phy/marvell.c Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com> Cc: Kumar Gala <galak@kernel.crashing.org>
2011-10-27 18:52:09 +00:00
reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
if (reg & MIIM_88E1111_HWCFG_FIBER_COPPER_RES)
reg |= MIIM_88E1111_HWCFG_MODE_FIBER_RGMII;
else
reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RGMII;
phy_write(phydev,
net: phy: marvell: Fix style violations Fix some style violations (mostly wrong indentions) in the Marvell PHY driver. Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-15 10:08:24 +00:00
MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR, reg);
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-08 02:56:05 +00:00
}
Phy/Marvell: Rewrite the MV88E1111 phy config function based on kernel code The original m88e1111s_config() does not do the SGMII mode initialization and is buggy. Rewrite the function according to 3.0.6 kernel function m88e1111_config_init() in drivers/net/phy/marvell.c Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com> Cc: Kumar Gala <galak@kernel.crashing.org>
2011-10-27 18:52:09 +00:00
if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
reg = phy_read(phydev,
net: phy: marvell: Fix style violations Fix some style violations (mostly wrong indentions) in the Marvell PHY driver. Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-15 10:08:24 +00:00
MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR);
Phy/Marvell: Rewrite the MV88E1111 phy config function based on kernel code The original m88e1111s_config() does not do the SGMII mode initialization and is buggy. Rewrite the function according to 3.0.6 kernel function m88e1111_config_init() in drivers/net/phy/marvell.c Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com> Cc: Kumar Gala <galak@kernel.crashing.org>
2011-10-27 18:52:09 +00:00
reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
reg |= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK;
reg |= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
phy_write(phydev, MDIO_DEVAD_NONE,
net: phy: marvell: Fix style violations Fix some style violations (mostly wrong indentions) in the Marvell PHY driver. Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-15 10:08:24 +00:00
MIIM_88E1111_PHY_EXT_SR, reg);
Phy/Marvell: Rewrite the MV88E1111 phy config function based on kernel code The original m88e1111s_config() does not do the SGMII mode initialization and is buggy. Rewrite the function according to 3.0.6 kernel function m88e1111_config_init() in drivers/net/phy/marvell.c Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com> Cc: Kumar Gala <galak@kernel.crashing.org>
2011-10-27 18:52:09 +00:00
}
if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
reg = phy_read(phydev,
net: phy: marvell: Fix style violations Fix some style violations (mostly wrong indentions) in the Marvell PHY driver. Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-15 10:08:24 +00:00
MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR);
Phy/Marvell: Rewrite the MV88E1111 phy config function based on kernel code The original m88e1111s_config() does not do the SGMII mode initialization and is buggy. Rewrite the function according to 3.0.6 kernel function m88e1111_config_init() in drivers/net/phy/marvell.c Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com> Cc: Kumar Gala <galak@kernel.crashing.org>
2011-10-27 18:52:09 +00:00
reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY);
phy_write(phydev,
net: phy: marvell: Fix style violations Fix some style violations (mostly wrong indentions) in the Marvell PHY driver. Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-15 10:08:24 +00:00
MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg);
Phy/Marvell: Rewrite the MV88E1111 phy config function based on kernel code The original m88e1111s_config() does not do the SGMII mode initialization and is buggy. Rewrite the function according to 3.0.6 kernel function m88e1111_config_init() in drivers/net/phy/marvell.c Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com> Cc: Kumar Gala <galak@kernel.crashing.org>
2011-10-27 18:52:09 +00:00
reg = phy_read(phydev, MDIO_DEVAD_NONE,
net: phy: marvell: Fix style violations Fix some style violations (mostly wrong indentions) in the Marvell PHY driver. Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-15 10:08:24 +00:00
MIIM_88E1111_PHY_EXT_SR);
Phy/Marvell: Rewrite the MV88E1111 phy config function based on kernel code The original m88e1111s_config() does not do the SGMII mode initialization and is buggy. Rewrite the function according to 3.0.6 kernel function m88e1111_config_init() in drivers/net/phy/marvell.c Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com> Cc: Kumar Gala <galak@kernel.crashing.org>
2011-10-27 18:52:09 +00:00
reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK |
MIIM_88E1111_HWCFG_FIBER_COPPER_RES);
reg |= 0x7 | MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
phy_write(phydev, MDIO_DEVAD_NONE,
net: phy: marvell: Fix style violations Fix some style violations (mostly wrong indentions) in the Marvell PHY driver. Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-15 10:08:24 +00:00
MIIM_88E1111_PHY_EXT_SR, reg);
Phy/Marvell: Rewrite the MV88E1111 phy config function based on kernel code The original m88e1111s_config() does not do the SGMII mode initialization and is buggy. Rewrite the function according to 3.0.6 kernel function m88e1111_config_init() in drivers/net/phy/marvell.c Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com> Cc: Kumar Gala <galak@kernel.crashing.org>
2011-10-27 18:52:09 +00:00
/* soft reset */
net: phy: marvell: Call phy_reset() where possible Instead of coding the soft PHY reset function multiple times in marvell.c, lets call the common phy_reset() function from phy.c. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefan Agner <stefan@agner.ch> Cc: Hao Zhang <hzhang@ti.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Andy Fleming <afleming@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-02-10 06:06:05 +00:00
phy_reset(phydev);
Phy/Marvell: Rewrite the MV88E1111 phy config function based on kernel code The original m88e1111s_config() does not do the SGMII mode initialization and is buggy. Rewrite the function according to 3.0.6 kernel function m88e1111_config_init() in drivers/net/phy/marvell.c Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com> Cc: Kumar Gala <galak@kernel.crashing.org>
2011-10-27 18:52:09 +00:00
reg = phy_read(phydev, MDIO_DEVAD_NONE,
net: phy: marvell: Fix style violations Fix some style violations (mostly wrong indentions) in the Marvell PHY driver. Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-15 10:08:24 +00:00
MIIM_88E1111_PHY_EXT_SR);
Phy/Marvell: Rewrite the MV88E1111 phy config function based on kernel code The original m88e1111s_config() does not do the SGMII mode initialization and is buggy. Rewrite the function according to 3.0.6 kernel function m88e1111_config_init() in drivers/net/phy/marvell.c Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com> Cc: Kumar Gala <galak@kernel.crashing.org>
2011-10-27 18:52:09 +00:00
reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK |
net: phy: marvell: Fix style violations Fix some style violations (mostly wrong indentions) in the Marvell PHY driver. Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-15 10:08:24 +00:00
MIIM_88E1111_HWCFG_FIBER_COPPER_RES);
Phy/Marvell: Rewrite the MV88E1111 phy config function based on kernel code The original m88e1111s_config() does not do the SGMII mode initialization and is buggy. Rewrite the function according to 3.0.6 kernel function m88e1111_config_init() in drivers/net/phy/marvell.c Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com> Cc: Kumar Gala <galak@kernel.crashing.org>
2011-10-27 18:52:09 +00:00
reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RTBI |
MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
phy_write(phydev, MDIO_DEVAD_NONE,
net: phy: marvell: Fix style violations Fix some style violations (mostly wrong indentions) in the Marvell PHY driver. Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-15 10:08:24 +00:00
MIIM_88E1111_PHY_EXT_SR, reg);
Phy/Marvell: Rewrite the MV88E1111 phy config function based on kernel code The original m88e1111s_config() does not do the SGMII mode initialization and is buggy. Rewrite the function according to 3.0.6 kernel function m88e1111_config_init() in drivers/net/phy/marvell.c Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com> Cc: Kumar Gala <galak@kernel.crashing.org>
2011-10-27 18:52:09 +00:00
}
/* soft reset */
net: phy: marvell: Call phy_reset() where possible Instead of coding the soft PHY reset function multiple times in marvell.c, lets call the common phy_reset() function from phy.c. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefan Agner <stefan@agner.ch> Cc: Hao Zhang <hzhang@ti.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Andy Fleming <afleming@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-02-10 06:06:05 +00:00
phy_reset(phydev);
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-08 02:56:05 +00:00
net: phy: marvell: Support reg config via "marvell, reg-init" DT property This patch adds support for the "marvell,reg-init" DT property, which is used to describe board specific Marvell PHY register configurations in the board dts file. This DT property is supported in the Linux Kernel since a longer time. Adding it to U-Boot now, enables the boards which describe the register settings in their DT files here as well. I've included calling this marvell_of_reg_init() to all foo_config() functions in this patch as well. If CONFIG_DM_ETH is not set, there is no ofnode, or no "marvell,reg-init" property, the PHY initialization is unchanged. The function marvell_of_reg_init() is a port of the Linux version. Please note that I explicitly did not add error checking and handling to the U-Boot version, as this is basically not done for phy_read/write in this Marvell PHY code. This will be used by the upcoming ethernet support on the MIPS Octeon EBB 7304 board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Marek Behún <marek.behun@nic.cz> Reviewed-by: Marek Behún <marek.behun@nic.cz>
2022-03-31 09:43:06 +00:00
marvell_of_reg_init(phydev);
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-08 02:56:05 +00:00
genphy_config_aneg(phydev);
net: phy: marvell: Fix problem with phy_reset() clearing BMCR With commit a058052c [net: phy: do not read configuration register on reset], phy_reset() will clear the BMCR register. Resulting in bit 12 being cleared (A/N enable). This leads to autonegotiation link problems, at least on the Marvell Armada ClearFog board. I suspect that other boards using this driver will be affected as well. At the of m88e1111s_config(), phy_reset() is called. This is not needed for the PHY to load the changed configuration, as phy_reset() is called a few lines before already. So lets call genphy_restart_aneg() here instead to start the AN correctly. Tested on clearfog. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefan Agner <stefan@agner.ch> Cc: Hao Zhang <hzhang@ti.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Andy Fleming <afleming@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-02-10 06:06:06 +00:00
genphy_restart_aneg(phydev);
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-08 02:56:05 +00:00
return 0;
}
net: phy: marvell: add errata w/a for 88E151* chips As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512/88E1514 Rev A0, Errata Section 3.1 Marvell PHY has an errata which requires that certain registers get written in order to restart autonegotiation. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Reviewed-by: Stefan Roese <sr@denx.de>
2014-10-30 16:59:43 +00:00
/**
net: phy: marvell: Unify 88E151x series phy_driver The PHY models of the Marvell 88E151x series are not reliably distinguishable by their uid / PHY identifiers. The 88E1510, 88E1512, 88E1514 and 88E1518 all have the same OUI and model number and bits 3:0 in the PHY Identifier 2 (Page 0, Reg 3) are described as HW revision number, but both 88E1510 and 88E1518 PHYs were observed with the same HW rev number (1). Before commit 83cfbeb0df9f ("net: phy: Fix mask so that we can identify Marvell 88E1518"), the 88E151x were detected because the HW revision bits were masked from the uid. After that change, 88E1510/12/18 were all detected as 88E1518 and the 88E1510 specific code was no longer run. I modified the mask to again ignore all four HW revision bits, removed the 88E1510 specific code (board-specific LED/INTn setup), which was not called since late 2016 anyway and renamed the config function and phy_driver struct to the better fitting 88e151x. The uid and mask bits 3:0 are now again the same as in the Linux kernel. Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com>
2020-02-24 19:52:20 +00:00
* m88e151x_phy_writebits - write bits to a register
net: phy: marvell: add errata w/a for 88E151* chips As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512/88E1514 Rev A0, Errata Section 3.1 Marvell PHY has an errata which requires that certain registers get written in order to restart autonegotiation. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Reviewed-by: Stefan Roese <sr@denx.de>
2014-10-30 16:59:43 +00:00
*/
net: phy: marvell: Unify 88E151x series phy_driver The PHY models of the Marvell 88E151x series are not reliably distinguishable by their uid / PHY identifiers. The 88E1510, 88E1512, 88E1514 and 88E1518 all have the same OUI and model number and bits 3:0 in the PHY Identifier 2 (Page 0, Reg 3) are described as HW revision number, but both 88E1510 and 88E1518 PHYs were observed with the same HW rev number (1). Before commit 83cfbeb0df9f ("net: phy: Fix mask so that we can identify Marvell 88E1518"), the 88E151x were detected because the HW revision bits were masked from the uid. After that change, 88E1510/12/18 were all detected as 88E1518 and the 88E1510 specific code was no longer run. I modified the mask to again ignore all four HW revision bits, removed the 88E1510 specific code (board-specific LED/INTn setup), which was not called since late 2016 anyway and renamed the config function and phy_driver struct to the better fitting 88e151x. The uid and mask bits 3:0 are now again the same as in the Linux kernel. Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com>
2020-02-24 19:52:20 +00:00
void m88e151x_phy_writebits(struct phy_device *phydev,
net: phy: marvell: Fix style violations Fix some style violations (mostly wrong indentions) in the Marvell PHY driver. Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-15 10:08:24 +00:00
u8 reg_num, u16 offset, u16 len, u16 data)
net: phy: marvell: add errata w/a for 88E151* chips As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512/88E1514 Rev A0, Errata Section 3.1 Marvell PHY has an errata which requires that certain registers get written in order to restart autonegotiation. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Reviewed-by: Stefan Roese <sr@denx.de>
2014-10-30 16:59:43 +00:00
{
u16 reg, mask;
if ((len + offset) >= 16)
mask = 0 - (1 << offset);
else
mask = (1 << (len + offset)) - (1 << offset);
reg = phy_read(phydev, MDIO_DEVAD_NONE, reg_num);
reg &= ~mask;
reg |= data << offset;
phy_write(phydev, MDIO_DEVAD_NONE, reg_num, reg);
}
net: phy: marvell: Unify 88E151x series phy_driver The PHY models of the Marvell 88E151x series are not reliably distinguishable by their uid / PHY identifiers. The 88E1510, 88E1512, 88E1514 and 88E1518 all have the same OUI and model number and bits 3:0 in the PHY Identifier 2 (Page 0, Reg 3) are described as HW revision number, but both 88E1510 and 88E1518 PHYs were observed with the same HW rev number (1). Before commit 83cfbeb0df9f ("net: phy: Fix mask so that we can identify Marvell 88E1518"), the 88E151x were detected because the HW revision bits were masked from the uid. After that change, 88E1510/12/18 were all detected as 88E1518 and the 88E1510 specific code was no longer run. I modified the mask to again ignore all four HW revision bits, removed the 88E1510 specific code (board-specific LED/INTn setup), which was not called since late 2016 anyway and renamed the config function and phy_driver struct to the better fitting 88e151x. The uid and mask bits 3:0 are now again the same as in the Linux kernel. Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com>
2020-02-24 19:52:20 +00:00
static int m88e151x_config(struct phy_device *phydev)
net: phy: marvell: add errata w/a for 88E151* chips As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512/88E1514 Rev A0, Errata Section 3.1 Marvell PHY has an errata which requires that certain registers get written in order to restart autonegotiation. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Reviewed-by: Stefan Roese <sr@denx.de>
2014-10-30 16:59:43 +00:00
{
net: phy: marvell 88e151x: Fix handling of RGMII interface types The 88E1518 code is programming the wrong registers for rgmii-id, rgmii-txid and rgmii-rxid interfaces. Since the PHY defaults to rgmii-id, it would appear that the code was previously only used with sgmii and rgmii-id interfaces. Tested on 88E1512 PHY in rgmii-id mode which is from the same family as 88E1518. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-05-24 13:43:06 +00:00
u16 reg;
net: phy: marvell: add errata w/a for 88E151* chips As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512/88E1514 Rev A0, Errata Section 3.1 Marvell PHY has an errata which requires that certain registers get written in order to restart autonegotiation. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Reviewed-by: Stefan Roese <sr@denx.de>
2014-10-30 16:59:43 +00:00
/*
* As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512
* /88E1514 Rev A0, Errata Section 3.1
*/
net: Improve 88E151x PHY initialization - The EEE fixup magic should also be enabled for RGMII - Improved comments Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Hao Zhang <hzhang@ti.com> Cc: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-06-06 12:44:57 +00:00
/* EEE initialization */
net: phy: Improve the Marvell 151x constants Use some constants for the phy configuration instead of so many magic numbers. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2016-12-09 17:54:39 +00:00
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00ff);
net: Improve 88E151x PHY initialization - The EEE fixup magic should also be enabled for RGMII - Improved comments Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Hao Zhang <hzhang@ti.com> Cc: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-06-06 12:44:57 +00:00
phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x214B);
phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2144);
phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x0C28);
phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2146);
phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xB233);
phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x214D);
phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xCC0C);
phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2159);
net: phy: Improve the Marvell 151x constants Use some constants for the phy configuration instead of so many magic numbers. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2016-12-09 17:54:39 +00:00
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
net: Improve 88E151x PHY initialization - The EEE fixup magic should also be enabled for RGMII - Improved comments Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Hao Zhang <hzhang@ti.com> Cc: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-06-06 12:44:57 +00:00
/* SGMII-to-Copper mode initialization */
net: phy: marvell: add errata w/a for 88E151* chips As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512/88E1514 Rev A0, Errata Section 3.1 Marvell PHY has an errata which requires that certain registers get written in order to restart autonegotiation. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Reviewed-by: Stefan Roese <sr@denx.de>
2014-10-30 16:59:43 +00:00
if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
net: Improve 88E151x PHY initialization - The EEE fixup magic should also be enabled for RGMII - Improved comments Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Hao Zhang <hzhang@ti.com> Cc: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-06-06 12:44:57 +00:00
/* Select page 18 */
net: phy: Improve the Marvell 151x constants Use some constants for the phy configuration instead of so many magic numbers. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2016-12-09 17:54:39 +00:00
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 18);
net: Improve 88E151x PHY initialization - The EEE fixup magic should also be enabled for RGMII - Improved comments Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Hao Zhang <hzhang@ti.com> Cc: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-06-06 12:44:57 +00:00
/* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */
net: phy: marvell: Unify 88E151x series phy_driver The PHY models of the Marvell 88E151x series are not reliably distinguishable by their uid / PHY identifiers. The 88E1510, 88E1512, 88E1514 and 88E1518 all have the same OUI and model number and bits 3:0 in the PHY Identifier 2 (Page 0, Reg 3) are described as HW revision number, but both 88E1510 and 88E1518 PHYs were observed with the same HW rev number (1). Before commit 83cfbeb0df9f ("net: phy: Fix mask so that we can identify Marvell 88E1518"), the 88E151x were detected because the HW revision bits were masked from the uid. After that change, 88E1510/12/18 were all detected as 88E1518 and the 88E1510 specific code was no longer run. I modified the mask to again ignore all four HW revision bits, removed the 88E1510 specific code (board-specific LED/INTn setup), which was not called since late 2016 anyway and renamed the config function and phy_driver struct to the better fitting 88e151x. The uid and mask bits 3:0 are now again the same as in the Linux kernel. Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com>
2020-02-24 19:52:20 +00:00
m88e151x_phy_writebits(phydev, MIIM_88E151x_GENERAL_CTRL,
net: phy: Improve the Marvell 151x constants Use some constants for the phy configuration instead of so many magic numbers. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2016-12-09 17:54:39 +00:00
0, 3, MIIM_88E151x_MODE_SGMII);
net: phy: marvell: add errata w/a for 88E151* chips As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512/88E1514 Rev A0, Errata Section 3.1 Marvell PHY has an errata which requires that certain registers get written in order to restart autonegotiation. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Reviewed-by: Stefan Roese <sr@denx.de>
2014-10-30 16:59:43 +00:00
net: Improve 88E151x PHY initialization - The EEE fixup magic should also be enabled for RGMII - Improved comments Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Hao Zhang <hzhang@ti.com> Cc: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-06-06 12:44:57 +00:00
/* PHY reset is necessary after changing MODE[2:0] */
net: phy: marvell: Unify 88E151x series phy_driver The PHY models of the Marvell 88E151x series are not reliably distinguishable by their uid / PHY identifiers. The 88E1510, 88E1512, 88E1514 and 88E1518 all have the same OUI and model number and bits 3:0 in the PHY Identifier 2 (Page 0, Reg 3) are described as HW revision number, but both 88E1510 and 88E1518 PHYs were observed with the same HW rev number (1). Before commit 83cfbeb0df9f ("net: phy: Fix mask so that we can identify Marvell 88E1518"), the 88E151x were detected because the HW revision bits were masked from the uid. After that change, 88E1510/12/18 were all detected as 88E1518 and the 88E1510 specific code was no longer run. I modified the mask to again ignore all four HW revision bits, removed the 88E1510 specific code (board-specific LED/INTn setup), which was not called since late 2016 anyway and renamed the config function and phy_driver struct to the better fitting 88e151x. The uid and mask bits 3:0 are now again the same as in the Linux kernel. Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com>
2020-02-24 19:52:20 +00:00
m88e151x_phy_writebits(phydev, MIIM_88E151x_GENERAL_CTRL,
net: phy: Improve the Marvell 151x constants Use some constants for the phy configuration instead of so many magic numbers. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2016-12-09 17:54:39 +00:00
MIIM_88E151x_RESET_OFFS, 1, 1);
net: Improve 88E151x PHY initialization - The EEE fixup magic should also be enabled for RGMII - Improved comments Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Hao Zhang <hzhang@ti.com> Cc: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-06-06 12:44:57 +00:00
/* Reset page selection */
net: phy: Improve the Marvell 151x constants Use some constants for the phy configuration instead of so many magic numbers. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2016-12-09 17:54:39 +00:00
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0);
net: Improve 88E151x PHY initialization - The EEE fixup magic should also be enabled for RGMII - Improved comments Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Hao Zhang <hzhang@ti.com> Cc: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-06-06 12:44:57 +00:00
net: phy: marvell: add errata w/a for 88E151* chips As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512/88E1514 Rev A0, Errata Section 3.1 Marvell PHY has an errata which requires that certain registers get written in order to restart autonegotiation. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Reviewed-by: Stefan Roese <sr@denx.de>
2014-10-30 16:59:43 +00:00
udelay(100);
}
net: phy: marvell 88e151x: Fix handling of RGMII interface types The 88E1518 code is programming the wrong registers for rgmii-id, rgmii-txid and rgmii-rxid interfaces. Since the PHY defaults to rgmii-id, it would appear that the code was previously only used with sgmii and rgmii-id interfaces. Tested on 88E1512 PHY in rgmii-id mode which is from the same family as 88E1518. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-05-24 13:43:06 +00:00
if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
reg = phy_read(phydev, MDIO_DEVAD_NONE,
MIIM_88E1111_PHY_EXT_SR);
reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
reg |= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK;
reg |= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
phy_write(phydev, MDIO_DEVAD_NONE,
MIIM_88E1111_PHY_EXT_SR, reg);
}
if (phy_interface_is_rgmii(phydev)) {
phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, 2);
reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E151x_PHY_MSCR);
reg &= ~MIIM_88E151x_RGMII_RXTX_DELAY;
net: phy: marvell 88e151x: Fix handling of bare RGMII interface type Commit 68e6ecadc551 ("net: phy: marvell 88e151x: Fix handling of RGMII interface types") fixed the initialization of 88e151x phys, but made it so that interfaces of type PHY_INTERFACE_MODE_RGMII had both RX and TX delay bits cleared. The default (like in m88e1111s_config) is to have both bits set. Hence, this patch changes the behavior in the PHY_INTERFACE_MODE_RGMII case so that both bits are set. Signed-off-by: Mario Six <mario.six@gdsys.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15 10:08:25 +00:00
if (phydev->interface == PHY_INTERFACE_MODE_RGMII ||
phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
net: phy: marvell 88e151x: Fix handling of RGMII interface types The 88E1518 code is programming the wrong registers for rgmii-id, rgmii-txid and rgmii-rxid interfaces. Since the PHY defaults to rgmii-id, it would appear that the code was previously only used with sgmii and rgmii-id interfaces. Tested on 88E1512 PHY in rgmii-id mode which is from the same family as 88E1518. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-05-24 13:43:06 +00:00
reg |= MIIM_88E151x_RGMII_RXTX_DELAY;
else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
reg |= MIIM_88E151x_RGMII_RX_DELAY;
else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
reg |= MIIM_88E151x_RGMII_TX_DELAY;
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E151x_PHY_MSCR, reg);
phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, 0);
}
/* soft reset */
phy_reset(phydev);
net: phy: marvell: Support reg config via "marvell, reg-init" DT property This patch adds support for the "marvell,reg-init" DT property, which is used to describe board specific Marvell PHY register configurations in the board dts file. This DT property is supported in the Linux Kernel since a longer time. Adding it to U-Boot now, enables the boards which describe the register settings in their DT files here as well. I've included calling this marvell_of_reg_init() to all foo_config() functions in this patch as well. If CONFIG_DM_ETH is not set, there is no ofnode, or no "marvell,reg-init" property, the PHY initialization is unchanged. The function marvell_of_reg_init() is a port of the Linux version. Please note that I explicitly did not add error checking and handling to the U-Boot version, as this is basically not done for phy_read/write in this Marvell PHY code. This will be used by the upcoming ethernet support on the MIPS Octeon EBB 7304 board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Marek Behún <marek.behun@nic.cz> Reviewed-by: Marek Behún <marek.behun@nic.cz>
2022-03-31 09:43:06 +00:00
marvell_of_reg_init(phydev);
net: phy: marvell 88e151x: Fix handling of RGMII interface types The 88E1518 code is programming the wrong registers for rgmii-id, rgmii-txid and rgmii-rxid interfaces. Since the PHY defaults to rgmii-id, it would appear that the code was previously only used with sgmii and rgmii-id interfaces. Tested on 88E1512 PHY in rgmii-id mode which is from the same family as 88E1518. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-05-24 13:43:06 +00:00
genphy_config_aneg(phydev);
genphy_restart_aneg(phydev);
return 0;
net: phy: marvell: add errata w/a for 88E151* chips As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512/88E1514 Rev A0, Errata Section 3.1 Marvell PHY has an errata which requires that certain registers get written in order to restart autonegotiation. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Reviewed-by: Stefan Roese <sr@denx.de>
2014-10-30 16:59:43 +00:00
}
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-08 02:56:05 +00:00
/* Marvell 88E1118 */
static int m88e1118_config(struct phy_device *phydev)
{
/* Change Page Number */
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0002);
/* Delay RGMII TX and RX */
phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x1070);
/* Change Page Number */
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0003);
/* Adjust LED control */
phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x021e);
/* Change Page Number */
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
net: phy: marvell: Support reg config via "marvell, reg-init" DT property This patch adds support for the "marvell,reg-init" DT property, which is used to describe board specific Marvell PHY register configurations in the board dts file. This DT property is supported in the Linux Kernel since a longer time. Adding it to U-Boot now, enables the boards which describe the register settings in their DT files here as well. I've included calling this marvell_of_reg_init() to all foo_config() functions in this patch as well. If CONFIG_DM_ETH is not set, there is no ofnode, or no "marvell,reg-init" property, the PHY initialization is unchanged. The function marvell_of_reg_init() is a port of the Linux version. Please note that I explicitly did not add error checking and handling to the U-Boot version, as this is basically not done for phy_read/write in this Marvell PHY code. This will be used by the upcoming ethernet support on the MIPS Octeon EBB 7304 board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Marek Behún <marek.behun@nic.cz> Reviewed-by: Marek Behún <marek.behun@nic.cz>
2022-03-31 09:43:06 +00:00
marvell_of_reg_init(phydev);
phy: marvell: Do not reset phy after negotiation The patch "net: phy: do not read configuration register on reset" (sha1: a058052c358c3ecf5f394ff37def6a45eb26768c) was causing regression on zynq zc702 board where Marwell 88e1118 phy was resetted after negotiation was setup. Phy reset is done pretty early in phy_connect_dev() and doens't need to be called again in phy code. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-05-18 12:46:28 +00:00
return genphy_config_aneg(phydev);
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-08 02:56:05 +00:00
}
static int m88e1118_startup(struct phy_device *phydev)
{
net: phy: Handle phy_startup() error codes properly Propagate error code from genphy_update_link() to phy startup(). Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Stephen Warren <swarren@nvidia.com>
2016-05-18 10:46:12 +00:00
int ret;
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-08 02:56:05 +00:00
/* Change Page Number */
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
net: phy: Handle phy_startup() error codes properly Propagate error code from genphy_update_link() to phy startup(). Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Stephen Warren <swarren@nvidia.com>
2016-05-18 10:46:12 +00:00
ret = genphy_update_link(phydev);
if (ret)
return ret;
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-08 02:56:05 +00:00
net: phy: Handle phy_startup() error codes properly Propagate error code from genphy_update_link() to phy startup(). Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Stephen Warren <swarren@nvidia.com>
2016-05-18 10:46:12 +00:00
return m88e1xxx_parse_status(phydev);
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-08 02:56:05 +00:00
}
/* Marvell 88E1121R */
static int m88e1121_config(struct phy_device *phydev)
{
int pg;
net: phy: marvell: Support reg config via "marvell, reg-init" DT property This patch adds support for the "marvell,reg-init" DT property, which is used to describe board specific Marvell PHY register configurations in the board dts file. This DT property is supported in the Linux Kernel since a longer time. Adding it to U-Boot now, enables the boards which describe the register settings in their DT files here as well. I've included calling this marvell_of_reg_init() to all foo_config() functions in this patch as well. If CONFIG_DM_ETH is not set, there is no ofnode, or no "marvell,reg-init" property, the PHY initialization is unchanged. The function marvell_of_reg_init() is a port of the Linux version. Please note that I explicitly did not add error checking and handling to the U-Boot version, as this is basically not done for phy_read/write in this Marvell PHY code. This will be used by the upcoming ethernet support on the MIPS Octeon EBB 7304 board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Marek Behún <marek.behun@nic.cz> Reviewed-by: Marek Behún <marek.behun@nic.cz>
2022-03-31 09:43:06 +00:00
marvell_of_reg_init(phydev);
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-08 02:56:05 +00:00
/* Configure the PHY */
genphy_config_aneg(phydev);
/* Switch the page to access the led register */
pg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE);
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE,
net: phy: marvell: Fix style violations Fix some style violations (mostly wrong indentions) in the Marvell PHY driver. Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-15 10:08:24 +00:00
MIIM_88E1121_PHY_LED_PAGE);
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-08 02:56:05 +00:00
/* Configure leds */
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_LED_CTRL,
net: phy: marvell: Fix style violations Fix some style violations (mostly wrong indentions) in the Marvell PHY driver. Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-15 10:08:24 +00:00
MIIM_88E1121_PHY_LED_DEF);
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-08 02:56:05 +00:00
/* Restore the page pointer */
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE, pg);
/* Disable IRQs and de-assert interrupt */
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_EN, 0);
phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_STATUS);
return 0;
}
/* Marvell 88E1145 */
static int m88e1145_config(struct phy_device *phydev)
{
int reg;
/* Errata E0, E1 */
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x001b);
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0x418f);
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x0016);
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0xa2da);
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_SCR,
net: phy: marvell: Fix style violations Fix some style violations (mostly wrong indentions) in the Marvell PHY driver. Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-15 10:08:24 +00:00
MIIM_88E1xxx_PHY_MDI_X_AUTO);
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-08 02:56:05 +00:00
reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR);
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
reg |= MIIM_M88E1145_RGMII_RX_DELAY |
MIIM_M88E1145_RGMII_TX_DELAY;
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR, reg);
net: phy: marvell: Support reg config via "marvell, reg-init" DT property This patch adds support for the "marvell,reg-init" DT property, which is used to describe board specific Marvell PHY register configurations in the board dts file. This DT property is supported in the Linux Kernel since a longer time. Adding it to U-Boot now, enables the boards which describe the register settings in their DT files here as well. I've included calling this marvell_of_reg_init() to all foo_config() functions in this patch as well. If CONFIG_DM_ETH is not set, there is no ofnode, or no "marvell,reg-init" property, the PHY initialization is unchanged. The function marvell_of_reg_init() is a port of the Linux version. Please note that I explicitly did not add error checking and handling to the U-Boot version, as this is basically not done for phy_read/write in this Marvell PHY code. This will be used by the upcoming ethernet support on the MIPS Octeon EBB 7304 board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Marek Behún <marek.behun@nic.cz> Reviewed-by: Marek Behún <marek.behun@nic.cz>
2022-03-31 09:43:06 +00:00
marvell_of_reg_init(phydev);
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-08 02:56:05 +00:00
genphy_config_aneg(phydev);
net: phy: marvell: Fix init function for m88e1145 Commit a058052c changed the generic phy_reset() to clear all bits in BMCR. This inevitably clears the ANEG bit. m88e1145 requires any change to ANEG bit to be followed by a software reset. This seems to be different from other PHYs. Implement read-modify-write procedure for this PHY init. Signed-off-by: York Sun <york.sun@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-06-06 16:22:40 +00:00
/* soft reset */
reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
reg |= BMCR_RESET;
phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg);
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-08 02:56:05 +00:00
return 0;
}
static int m88e1145_startup(struct phy_device *phydev)
{
net: phy: Handle phy_startup() error codes properly Propagate error code from genphy_update_link() to phy startup(). Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Stephen Warren <swarren@nvidia.com>
2016-05-18 10:46:12 +00:00
int ret;
ret = genphy_update_link(phydev);
if (ret)
return ret;
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-08 02:56:05 +00:00
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_LED_CONTROL,
net: phy: marvell: Fix style violations Fix some style violations (mostly wrong indentions) in the Marvell PHY driver. Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-15 10:08:24 +00:00
MIIM_88E1145_PHY_LED_DIRECT);
net: phy: Handle phy_startup() error codes properly Propagate error code from genphy_update_link() to phy startup(). Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Stephen Warren <swarren@nvidia.com>
2016-05-18 10:46:12 +00:00
return m88e1xxx_parse_status(phydev);
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-08 02:56:05 +00:00
}
/* Marvell 88E1149S */
static int m88e1149_config(struct phy_device *phydev)
{
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x1f);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c);
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x5);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x0);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
net: phy: marvell: Support reg config via "marvell, reg-init" DT property This patch adds support for the "marvell,reg-init" DT property, which is used to describe board specific Marvell PHY register configurations in the board dts file. This DT property is supported in the Linux Kernel since a longer time. Adding it to U-Boot now, enables the boards which describe the register settings in their DT files here as well. I've included calling this marvell_of_reg_init() to all foo_config() functions in this patch as well. If CONFIG_DM_ETH is not set, there is no ofnode, or no "marvell,reg-init" property, the PHY initialization is unchanged. The function marvell_of_reg_init() is a port of the Linux version. Please note that I explicitly did not add error checking and handling to the U-Boot version, as this is basically not done for phy_read/write in this Marvell PHY code. This will be used by the upcoming ethernet support on the MIPS Octeon EBB 7304 board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Marek Behún <marek.behun@nic.cz> Reviewed-by: Marek Behún <marek.behun@nic.cz>
2022-03-31 09:43:06 +00:00
marvell_of_reg_init(phydev);
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-08 02:56:05 +00:00
genphy_config_aneg(phydev);
phy_reset(phydev);
return 0;
}
net: phy: marvell: Add support for 88E1240 PHY This patch adds basic support for the Marvell 88E1240 PHY. This will be used by the upcoming ethernet support addition for the Marvell MIPS Octeon EBB7304 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Reviewed-by: Marek Behún <marek.behun@nic.cz>
2022-03-31 09:43:07 +00:00
/* Marvell 88E1240 */
static int m88e1240_config(struct phy_device *phydev)
{
marvell_of_reg_init(phydev);
genphy_config_aneg(phydev);
return 0;
}
NET: phy: add 88E1310 PHY initialization This adds PHY initialization for Marvell Alaska 88E1310 PHY. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2012-12-04 08:31:59 +00:00
/* Marvell 88E1310 */
static int m88e1310_config(struct phy_device *phydev)
{
u16 reg;
/* LED link and activity */
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003);
reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL);
reg = (reg & ~0xf) | 0x1;
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL, reg);
/* Set LED2/INT to INT mode, low active */
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003);
reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN);
reg = (reg & 0x77ff) | 0x0880;
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN, reg);
/* Set RGMII delay */
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0002);
reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL);
reg |= 0x0030;
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL, reg);
/* Ensure to return to page 0 */
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0000);
net: phy: marvell: Support reg config via "marvell, reg-init" DT property This patch adds support for the "marvell,reg-init" DT property, which is used to describe board specific Marvell PHY register configurations in the board dts file. This DT property is supported in the Linux Kernel since a longer time. Adding it to U-Boot now, enables the boards which describe the register settings in their DT files here as well. I've included calling this marvell_of_reg_init() to all foo_config() functions in this patch as well. If CONFIG_DM_ETH is not set, there is no ofnode, or no "marvell,reg-init" property, the PHY initialization is unchanged. The function marvell_of_reg_init() is a port of the Linux version. Please note that I explicitly did not add error checking and handling to the U-Boot version, as this is basically not done for phy_read/write in this Marvell PHY code. This will be used by the upcoming ethernet support on the MIPS Octeon EBB 7304 board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Marek Behún <marek.behun@nic.cz> Reviewed-by: Marek Behún <marek.behun@nic.cz>
2022-03-31 09:43:06 +00:00
marvell_of_reg_init(phydev);
net: phy: marvell: Do not reset 88e1310 after autoneg Commit a058052c "net: phy: do not read configuration register on reset", changes the behaviour of the phy_reset function such that the state of the BMCR register is not preserved during reset. Change the config function for the m88e1310 so that it does not do a reset after configuring auto-negotiation. Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Stefan Roese <sr@denx.de> Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Stefan Roese <sr@denx.de>
2016-06-03 13:16:17 +00:00
return genphy_config_aneg(phydev);
NET: phy: add 88E1310 PHY initialization This adds PHY initialization for Marvell Alaska 88E1310 PHY. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2012-12-04 08:31:59 +00:00
}
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-08 02:56:05 +00:00
net: phy: Support Marvell 88E1680 Add support for Marvell 88E1680 Integrated Octal 10/100/1000 Mbps Energy Efficient Ethernet Transceiver. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Stefan Roese <sr@denx.de>
2017-01-11 15:00:46 +00:00
static int m88e1680_config(struct phy_device *phydev)
{
/*
* As per Marvell Release Notes - Alaska V 88E1680 Rev A2
* Errata Section 4.1
*/
u16 reg;
int res;
/* Matrix LED mode (not neede if single LED mode is used */
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0004);
reg = phy_read(phydev, MDIO_DEVAD_NONE, 27);
reg |= (1 << 5);
phy_write(phydev, MDIO_DEVAD_NONE, 27, reg);
/* QSGMII TX amplitude change */
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00fd);
phy_write(phydev, MDIO_DEVAD_NONE, 8, 0x0b53);
phy_write(phydev, MDIO_DEVAD_NONE, 7, 0x200d);
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
/* EEE initialization */
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00ff);
phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xb030);
phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x215c);
phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x00fc);
phy_write(phydev, MDIO_DEVAD_NONE, 24, 0x888c);
phy_write(phydev, MDIO_DEVAD_NONE, 25, 0x888c);
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x9140);
net: phy: marvell: Support reg config via "marvell, reg-init" DT property This patch adds support for the "marvell,reg-init" DT property, which is used to describe board specific Marvell PHY register configurations in the board dts file. This DT property is supported in the Linux Kernel since a longer time. Adding it to U-Boot now, enables the boards which describe the register settings in their DT files here as well. I've included calling this marvell_of_reg_init() to all foo_config() functions in this patch as well. If CONFIG_DM_ETH is not set, there is no ofnode, or no "marvell,reg-init" property, the PHY initialization is unchanged. The function marvell_of_reg_init() is a port of the Linux version. Please note that I explicitly did not add error checking and handling to the U-Boot version, as this is basically not done for phy_read/write in this Marvell PHY code. This will be used by the upcoming ethernet support on the MIPS Octeon EBB 7304 board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Marek Behún <marek.behun@nic.cz> Reviewed-by: Marek Behún <marek.behun@nic.cz>
2022-03-31 09:43:06 +00:00
marvell_of_reg_init(phydev);
net: phy: Support Marvell 88E1680 Add support for Marvell 88E1680 Integrated Octal 10/100/1000 Mbps Energy Efficient Ethernet Transceiver. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Stefan Roese <sr@denx.de>
2017-01-11 15:00:46 +00:00
res = genphy_config_aneg(phydev);
if (res < 0)
return res;
/* soft reset */
reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
reg |= BMCR_RESET;
phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg);
return 0;
}
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-08 02:56:05 +00:00
static struct phy_driver M88E1011S_driver = {
.name = "Marvell 88E1011S",
.uid = 0x1410c60,
.mask = 0xffffff0,
.features = PHY_GBIT_FEATURES,
.config = &m88e1011s_config,
.startup = &m88e1011s_startup,
.shutdown = &genphy_shutdown,
};
static struct phy_driver M88E1111S_driver = {
.name = "Marvell 88E1111S",
.uid = 0x1410cc0,
.mask = 0xffffff0,
.features = PHY_GBIT_FEATURES,
.config = &m88e1111s_config,
.startup = &m88e1011s_startup,
.shutdown = &genphy_shutdown,
};
static struct phy_driver M88E1118_driver = {
.name = "Marvell 88E1118",
.uid = 0x1410e10,
.mask = 0xffffff0,
.features = PHY_GBIT_FEATURES,
.config = &m88e1118_config,
.startup = &m88e1118_startup,
.shutdown = &genphy_shutdown,
};
phy: Add support for Marvell 88E1118R Marvell 88E1118R has different uid then 88E1118. Signed-off-by: Michal Simek <monstr@monstr.eu> CC: Andy Fleming <afleming@freescale.com> CC: Zang Roy-R61911 <tie-fei.zang@freescale.com> CC: Kumar Gala <galak@kernel.crashing.org>
2012-08-07 02:23:07 +00:00
static struct phy_driver M88E1118R_driver = {
.name = "Marvell 88E1118R",
.uid = 0x1410e40,
.mask = 0xffffff0,
.features = PHY_GBIT_FEATURES,
.config = &m88e1118_config,
.startup = &m88e1118_startup,
.shutdown = &genphy_shutdown,
};
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-08 02:56:05 +00:00
static struct phy_driver M88E1121R_driver = {
.name = "Marvell 88E1121R",
.uid = 0x1410cb0,
.mask = 0xffffff0,
.features = PHY_GBIT_FEATURES,
.config = &m88e1121_config,
.startup = &genphy_startup,
.shutdown = &genphy_shutdown,
};
static struct phy_driver M88E1145_driver = {
.name = "Marvell 88E1145",
.uid = 0x1410cd0,
.mask = 0xffffff0,
.features = PHY_GBIT_FEATURES,
.config = &m88e1145_config,
.startup = &m88e1145_startup,
.shutdown = &genphy_shutdown,
};
static struct phy_driver M88E1149S_driver = {
.name = "Marvell 88E1149S",
.uid = 0x1410ca0,
.mask = 0xffffff0,
.features = PHY_GBIT_FEATURES,
.config = &m88e1149_config,
.startup = &m88e1011s_startup,
.shutdown = &genphy_shutdown,
};
net: phy: marvell: Add support for 88E1240 PHY This patch adds basic support for the Marvell 88E1240 PHY. This will be used by the upcoming ethernet support addition for the Marvell MIPS Octeon EBB7304 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Reviewed-by: Marek Behún <marek.behun@nic.cz>
2022-03-31 09:43:07 +00:00
static struct phy_driver M88E1240_driver = {
.name = "Marvell 88E1240",
.uid = 0x1410e30,
.mask = 0xffffff0,
.features = PHY_GBIT_FEATURES,
.config = &m88e1240_config,
.startup = &m88e1011s_startup,
.shutdown = &genphy_shutdown,
};
net: phy: marvell: Unify 88E151x series phy_driver The PHY models of the Marvell 88E151x series are not reliably distinguishable by their uid / PHY identifiers. The 88E1510, 88E1512, 88E1514 and 88E1518 all have the same OUI and model number and bits 3:0 in the PHY Identifier 2 (Page 0, Reg 3) are described as HW revision number, but both 88E1510 and 88E1518 PHYs were observed with the same HW rev number (1). Before commit 83cfbeb0df9f ("net: phy: Fix mask so that we can identify Marvell 88E1518"), the 88E151x were detected because the HW revision bits were masked from the uid. After that change, 88E1510/12/18 were all detected as 88E1518 and the 88E1510 specific code was no longer run. I modified the mask to again ignore all four HW revision bits, removed the 88E1510 specific code (board-specific LED/INTn setup), which was not called since late 2016 anyway and renamed the config function and phy_driver struct to the better fitting 88e151x. The uid and mask bits 3:0 are now again the same as in the Linux kernel. Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com>
2020-02-24 19:52:20 +00:00
static struct phy_driver M88E151x_driver = {
.name = "Marvell 88E151x",
net: phy: Add support for Marvell M88E1512 This device also works with the 88E1518 code, so we just adjust the UID mask accordingly. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-12-12 12:54:14 +00:00
.uid = 0x1410dd0,
net: phy: marvell: Unify 88E151x series phy_driver The PHY models of the Marvell 88E151x series are not reliably distinguishable by their uid / PHY identifiers. The 88E1510, 88E1512, 88E1514 and 88E1518 all have the same OUI and model number and bits 3:0 in the PHY Identifier 2 (Page 0, Reg 3) are described as HW revision number, but both 88E1510 and 88E1518 PHYs were observed with the same HW rev number (1). Before commit 83cfbeb0df9f ("net: phy: Fix mask so that we can identify Marvell 88E1518"), the 88E151x were detected because the HW revision bits were masked from the uid. After that change, 88E1510/12/18 were all detected as 88E1518 and the 88E1510 specific code was no longer run. I modified the mask to again ignore all four HW revision bits, removed the 88E1510 specific code (board-specific LED/INTn setup), which was not called since late 2016 anyway and renamed the config function and phy_driver struct to the better fitting 88e151x. The uid and mask bits 3:0 are now again the same as in the Linux kernel. Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com>
2020-02-24 19:52:20 +00:00
.mask = 0xffffff0,
net: phy: Define Marvell 88e1518 phy This phy is used on zedboard (xilinx zynq platform). Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
2012-10-15 12:03:00 +00:00
.features = PHY_GBIT_FEATURES,
net: phy: marvell: Unify 88E151x series phy_driver The PHY models of the Marvell 88E151x series are not reliably distinguishable by their uid / PHY identifiers. The 88E1510, 88E1512, 88E1514 and 88E1518 all have the same OUI and model number and bits 3:0 in the PHY Identifier 2 (Page 0, Reg 3) are described as HW revision number, but both 88E1510 and 88E1518 PHYs were observed with the same HW rev number (1). Before commit 83cfbeb0df9f ("net: phy: Fix mask so that we can identify Marvell 88E1518"), the 88E151x were detected because the HW revision bits were masked from the uid. After that change, 88E1510/12/18 were all detected as 88E1518 and the 88E1510 specific code was no longer run. I modified the mask to again ignore all four HW revision bits, removed the 88E1510 specific code (board-specific LED/INTn setup), which was not called since late 2016 anyway and renamed the config function and phy_driver struct to the better fitting 88e151x. The uid and mask bits 3:0 are now again the same as in the Linux kernel. Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com>
2020-02-24 19:52:20 +00:00
.config = &m88e151x_config,
net: phy: Define Marvell 88e1518 phy This phy is used on zedboard (xilinx zynq platform). Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
2012-10-15 12:03:00 +00:00
.startup = &m88e1011s_startup,
.shutdown = &genphy_shutdown,
net: phy: marvell: Add functions to read PHY's extended registers This commit allows extended Marvell registers to be read with: foo > mdio rx FEC 3.10 Reading from bus FEC PHY at address 0: 3.16 - 0x1063 foo > mdio wx FEC 3.10 0x1011 The above code changes the way ETH connector LEDs blink. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: York Sun <york.sun@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-10-30 21:57:53 +00:00
.readext = &m88e1xxx_phy_extread,
.writeext = &m88e1xxx_phy_extwrite,
net: phy: Define Marvell 88e1518 phy This phy is used on zedboard (xilinx zynq platform). Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
2012-10-15 12:03:00 +00:00
};
NET: phy: add 88E1310 PHY initialization This adds PHY initialization for Marvell Alaska 88E1310 PHY. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2012-12-04 08:31:59 +00:00
static struct phy_driver M88E1310_driver = {
.name = "Marvell 88E1310",
.uid = 0x01410e90,
.mask = 0xffffff0,
.features = PHY_GBIT_FEATURES,
.config = &m88e1310_config,
.startup = &m88e1011s_startup,
.shutdown = &genphy_shutdown,
};
net: phy: Support Marvell 88E1680 Add support for Marvell 88E1680 Integrated Octal 10/100/1000 Mbps Energy Efficient Ethernet Transceiver. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Stefan Roese <sr@denx.de>
2017-01-11 15:00:46 +00:00
static struct phy_driver M88E1680_driver = {
.name = "Marvell 88E1680",
.uid = 0x1410ed0,
.mask = 0xffffff0,
.features = PHY_GBIT_FEATURES,
.config = &m88e1680_config,
.startup = &genphy_startup,
.shutdown = &genphy_shutdown,
};
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-08 02:56:05 +00:00
int phy_marvell_init(void)
{
NET: phy: add 88E1310 PHY initialization This adds PHY initialization for Marvell Alaska 88E1310 PHY. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2012-12-04 08:31:59 +00:00
phy_register(&M88E1310_driver);
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-08 02:56:05 +00:00
phy_register(&M88E1149S_driver);
phy_register(&M88E1145_driver);
phy_register(&M88E1121R_driver);
phy_register(&M88E1118_driver);
phy: Add support for Marvell 88E1118R Marvell 88E1118R has different uid then 88E1118. Signed-off-by: Michal Simek <monstr@monstr.eu> CC: Andy Fleming <afleming@freescale.com> CC: Zang Roy-R61911 <tie-fei.zang@freescale.com> CC: Kumar Gala <galak@kernel.crashing.org>
2012-08-07 02:23:07 +00:00
phy_register(&M88E1118R_driver);
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-08 02:56:05 +00:00
phy_register(&M88E1111S_driver);
phy_register(&M88E1011S_driver);
net: phy: marvell: Add support for 88E1240 PHY This patch adds basic support for the Marvell 88E1240 PHY. This will be used by the upcoming ethernet support addition for the Marvell MIPS Octeon EBB7304 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Reviewed-by: Marek Behún <marek.behun@nic.cz>
2022-03-31 09:43:07 +00:00
phy_register(&M88E1240_driver);
net: phy: marvell: Unify 88E151x series phy_driver The PHY models of the Marvell 88E151x series are not reliably distinguishable by their uid / PHY identifiers. The 88E1510, 88E1512, 88E1514 and 88E1518 all have the same OUI and model number and bits 3:0 in the PHY Identifier 2 (Page 0, Reg 3) are described as HW revision number, but both 88E1510 and 88E1518 PHYs were observed with the same HW rev number (1). Before commit 83cfbeb0df9f ("net: phy: Fix mask so that we can identify Marvell 88E1518"), the 88E151x were detected because the HW revision bits were masked from the uid. After that change, 88E1510/12/18 were all detected as 88E1518 and the 88E1510 specific code was no longer run. I modified the mask to again ignore all four HW revision bits, removed the 88E1510 specific code (board-specific LED/INTn setup), which was not called since late 2016 anyway and renamed the config function and phy_driver struct to the better fitting 88e151x. The uid and mask bits 3:0 are now again the same as in the Linux kernel. Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com>
2020-02-24 19:52:20 +00:00
phy_register(&M88E151x_driver);
net: phy: Support Marvell 88E1680 Add support for Marvell 88E1680 Integrated Octal 10/100/1000 Mbps Energy Efficient Ethernet Transceiver. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Stefan Roese <sr@denx.de>
2017-01-11 15:00:46 +00:00
phy_register(&M88E1680_driver);
phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-08 02:56:05 +00:00
return 0;
}
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