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u-boot/arch/arm/dts/imx7d-sdb-u-boot.dtsi

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imx7: Disable CAAM Job Ring 0 Trying to boot a fitImage after a successful hab_auth_img operation causes the following error: ## Loading kernel from FIT Image at 88000000 ... Using 'conf-imx7d-smegw01.dtb' configuration Trying 'kernel-1' kernel subimage Description: Linux kernel Type: Kernel Image Compression: uncompressed Data Start: 0x8800010c Data Size: 9901752 Bytes = 9.4 MiB Architecture: ARM OS: Linux Load Address: 0x80800000 Entry Point: 0x80800000 Hash algo: sha256 Hash value: 28f8779bbf010780f16dd3d84ecb9b604c44c5c2cf7acd098c264a2d3f68e969 Verifying Hash Integrity ... sha256Error in SEC deq CAAM was not setup properly or it is faulty error! The reason for this error is that the BootROM uses the CAAM Job Ring 0, so disable its node in U-Boot to avoid the resource conflict. imx8m dtsi files also have the Job Ring 0 disable since the following kernel commit: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/arch?h=v6.5&id=dc9c1ceb555ff661e6fc1081434600771f29657c For a temporary solution, disable the Job Ring 0 in imx7s-u-boot.dtsi. Reported-by: Eduard Strehlau <eduard@lionizers.com> Signed-off-by: Fabio Estevam <festevam@denx.de>
2023-09-12 15:11:00 +00:00
#include "imx7s-u-boot.dtsi"
mx7dsabre: Enable DM_ETH Also sync device tree with v5.5-rc1 Signed-off-by: Joris Offouga <offougajoris@gmail.com>
2019-12-08 17:02:30 +00:00
&fec2 {
status = "disable";
};
mx7dsabre: Fix usbtog probe when use dfu or ums Before: => ums 0 mmc 0 UMS: LUN 0, dev 0, hwpart 0, sector 0x0, count 0x1dacc00 usb dr_mode not found CTRL+C - Operation aborted => dfu 0 mmc 0 usb dr_mode not found After : => ums 0 mmc 0 UMS: LUN 0, dev 0, hwpart 0, sector 0x0, count 0x1dacc00 => dfu 0 mmc 0 Signed-off-by: Joris Offouga <offougajoris@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2020-01-29 21:06:01 +00:00
&usbotg1 {
dr_mode = "peripheral";
};
ARM: dts: imx7d-sdb-u-boot: Fix usdhc1 UHS operation Commit 1a7904fdfa7d ("mmc: fsl_esdhc_imx: Use esdhc_soc_data flags to set host caps") exposed the following SD card error: U-Boot 2023.04-00652-g487e42f7bc5e (Apr 05 2023 - 22:14:21 -0300) CPU: Freescale i.MX7D rev1.0 1000 MHz (running at 792 MHz) CPU: Commercial temperature grade (0C to 95C) at 35C Reset cause: POR Model: Freescale i.MX7 SabreSD Board Board: i.MX7D SABRESD in non-secure mode DRAM: 1 GiB Core: 100 devices, 19 uclasses, devicetree: separate PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x10 MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... Card did not respond to voltage select! : -110 *** Warning - No block device, using default environment The reason of the problem, as explained by Ye Li: "When UHS is enabled in defconfig, the usdhc1 node in imx7d-sdb.dts does not configure pad for VSELECT, also the data pad should be set to 100Mhz/200Mhz pin states." Apply these changes into u-boot.dtsi for now. When these changes reach the Linux mainline imx7d-sdb, they can be dropped from u-boot.dtsi. This fixes UHS mode on the imx7d-sdb board. Suggested-by: Ye Li <ye.li@nxp.com> Signed-off-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-04-12 12:41:04 +00:00
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
};
&pinctrl_usdhc1 {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x59
MX7D_PAD_SD1_CLK__SD1_CLK 0x19
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
>;
};
&iomuxc {
pinctrl_usdhc1_gpio: usdhc1gpiogrp {
fsl,pins = <
MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */
MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */
MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */
MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */
>;
};
pinctrl_usdhc1_100mhz: usdhc1100mhzgrp {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
MX7D_PAD_SD1_CLK__SD1_CLK 0x1a
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
>;
};
pinctrl_usdhc1_200mhz: usdhc1200mhzgrp {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
>;
};
};
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