mirror of
https://github.com/AsahiLinux/u-boot
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117 lines
5 KiB
C
117 lines
5 KiB
C
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/*
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* File: include/asm-blackfin/arch-bf537/anomaly.h
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* Based on:
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* Author:
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*
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* Created:
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* Description:
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*
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* Rev:
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*
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* Modified:
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING.
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* If not, write to the Free Software Foundation,
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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/* This file shoule be up to date with:
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* - Revision J, June 1, 2006; ADSP-BF537 Blackfin Processor Anomaly List
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* - Revision I, June 1, 2006; ADSP-BF536 Blackfin Processor Anomaly List
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* - Revision J, June 1, 2006; ADSP-BF534 Blackfin Processor Anomaly List
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*/
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#ifndef _MACH_ANOMALY_H_
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#define _MACH_ANOMALY_H_
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/* We do not support 0.1 silicon - sorry */
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#if (defined(CONFIG_BF_REV_0_1))
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#error Kernel will not work on BF537/6/4 Version 0.1
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#endif
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#if (defined(CONFIG_BF_REV_0_3) || defined(CONFIG_BF_REV_0_2))
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#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
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slot1 and store of a P register in slot 2 is not
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supported */
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#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive
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Channel DMA stops */
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#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR
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registers. */
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#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out
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upper bits */
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#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame
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syncs */
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#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
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#define ANOMALY_05000247 /* CLKIN Buffer Output Enable Reset Behavior Is
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Changed */
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#endif
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#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
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SPORT external receive and transmit clocks. */
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#define ANOMALY_05000272 /* Certain data cache write through modes fail for
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VDDint <=0.9V */
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#define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */
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#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
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an edge is detected may clear interrupt */
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#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
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not restored */
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#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic
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control */
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#define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when
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killed in a particular stage */
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#endif
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#if defined(CONFIG_BF_REV_0_2)
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#define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or
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IDLE around a Change of Control causes
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unpredictable results */
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#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
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(TDM) */
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#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
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#define ANOMALY_05000252 /* EMAC Tx DMA error after an early frame abort */
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#endif
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#define ANOMALY_05000253 /* Maximum external clock speed for Timers */
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#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event
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interrupt not functional */
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#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
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#define ANOMALY_05000256 /* EMAC MDIO input latched on wrong MDC edge */
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#endif
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#define ANOMALY_05000257 /* An interrupt or exception during short Hardware
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loops may cause the instruction fetch unit to
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malfunction */
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#define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of
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the ICPLB Data registers differ */
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#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */
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#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */
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#define ANOMALY_05000262 /* Stores to data cache may be lost */
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#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */
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#define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE
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instruction will cause an infinite stall in the
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second to last instruction in a hardware loop */
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#define ANOMALY_05000268 /* Memory DMA error when peripheral DMA is running
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and non-zero DEB_TRAFFIC_PERIOD value */
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#define ANOMALY_05000270 /* High I/O activity causes the output voltage of the
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internal voltage regulator (VDDint) to decrease */
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#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
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an edge is detected may clear interrupt */
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#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause
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DMA system instability */
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#define ANOMALY_05000280 /* SPI Master boot mode does not work well with
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Atmel Dataflash devices */
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#endif /* CONFIG_BF_REV_0_2 */
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#endif /* _MACH_ANOMALY_H_ */
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