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u-boot/drivers/timer/Kconfig

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dm: implement a Timer uclass Implement a Timer uclass to work with lib/time.c. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org>
2015-10-09 05:46:34 +00:00
menu "Timer Support"
config TIMER
dm: timer: Fix several nits This changes 'Timer' to 'timer' at several places. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org>
2015-11-13 08:11:14 +00:00
bool "Enable driver model for timer drivers"
dm: implement a Timer uclass Implement a Timer uclass to work with lib/time.c. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org>
2015-10-09 05:46:34 +00:00
depends on DM
help
dm: timer: Fix several nits This changes 'Timer' to 'timer' at several places. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org>
2015-11-13 08:11:14 +00:00
Enable driver model for timer access. It uses the same API as
lib/time.c, but now implemented by the uclass. The first timer
dm: implement a Timer uclass Implement a Timer uclass to work with lib/time.c. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org>
2015-10-09 05:46:34 +00:00
will be used. The timer is usually a 32 bits free-running up
counter. There may be no real tick, and no timer interrupt.
dm: timer: normalise SPL and TPL support To fully support DM timer in SPL and TPL, we need a few things cleaned up and normalised: - inclusion of the uclass and drivers should be an all-or-nothing decision for each stage and under control of $(SPL_TPL_)TIMER instead of having the two-level configuration with TIMER and $(SPL_TPL_)TIMER_SUPPORT - when $(SPL_TPL_)TIMER is enabled, the ARMv8 generic timer code can not be compiled in This normalises configuration to $(SPL_TPL_)TIMER and moves the config options to drivers/timer/Kconfig (and cleans up the collateral damage to some defconfigs that had SPL_TIMER_SUPPORT enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 15:38:42 +00:00
config SPL_TIMER
bool "Enable driver model for timer drivers in SPL"
depends on TIMER && SPL
help
Enable support for timer drivers in SPL. These can be used to get
a timer value when in SPL, or perhaps for implementing a delay
function. This enables the drivers in drivers/timer as part of an
SPL build.
config TPL_TIMER
bool "Enable driver model for timer drivers in TPL"
depends on TIMER && TPL
help
Enable support for timer drivers in TPL. These can be used to get
a timer value when in TPL, or perhaps for implementing a delay
function. This enables the drivers in drivers/timer as part of an
TPL build.
timer: Provide an early timer In some cases the timer must be accessible before driver model is active. Examples include when using CONFIG_TRACE to trace U-Boot's execution before driver model is set up. Enable this option to use an early timer. These functions must be supported by your timer driver: timer_early_get_count() and timer_early_get_rate(). Signed-off-by: Simon Glass <sjg@chromium.org>
2016-02-24 16:14:49 +00:00
config TIMER_EARLY
bool "Allow timer to be used early in U-Boot"
depends on TIMER
Enable CONFIG_TIMER_EARLY with bootstage In initr_bootstage() we call bootstage_mark_name() which ends up calling timer_get_us(). This call happens before initr_dm(), which inits driver model. On x86 we set gd->timer to NULL in the transition from board_init_f() to board_init_r(). See board_init_f_r() for this assignment. So U-Boot knows there is no timer available in the period immediately after relocation. On x86 the timer_get_us() call is implemented as calls to get_ticks() and get_tbclk(). Both of these call dm_timer_init() to set up the timer, if gd->timer is NULL and the early timer is not available. However dm_timer_init() cannot succeed before initr_dm() is called. So it seems that on x86 if we want to use CONFIG_BOOTSTAGE we must enable CONFIG_TIMER_EARLY. Update the Kconfig to handle this. Note: On most architectures we can rely on the pre-relocation memory still being available, so that gd->timer pointers to a valid timer device and everything works correctly. Admittedly this is not strictly correct since the timer device is set up by pre-relocation U-Boot, but normally this is fine. On x86 the 'CAR' (cache-as-RAM) memory used by pre-relocation U-Boot disappears in board_init_f_r() and any attempt to access it will hang. This is the reason why we must mark the timer as invalid when we get to board_init_f_r(). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-09-02 23:02:24 +00:00
# initr_bootstage() requires a timer and is called before initr_dm()
# so only the early timer is available
default y if X86 && BOOTSTAGE
timer: Provide an early timer In some cases the timer must be accessible before driver model is active. Examples include when using CONFIG_TRACE to trace U-Boot's execution before driver model is set up. Enable this option to use an early timer. These functions must be supported by your timer driver: timer_early_get_count() and timer_early_get_rate(). Signed-off-by: Simon Glass <sjg@chromium.org>
2016-02-24 16:14:49 +00:00
help
In some cases the timer must be accessible before driver model is
active. Examples include when using CONFIG_TRACE to trace U-Boot's
execution before driver model is set up. Enable this option to
use an early timer. These functions must be supported by your timer
driver: timer_early_get_count() and timer_early_get_rate().
nios2: convert altera timer to driver model Convert altera timer to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com>
2015-10-22 14:28:53 +00:00
config ALTERA_TIMER
dm: timer: Fix several nits This changes 'Timer' to 'timer' at several places. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org>
2015-11-13 08:11:14 +00:00
bool "Altera timer support"
nios2: convert altera timer to driver model Convert altera timer to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com>
2015-10-22 14:28:53 +00:00
depends on TIMER
help
dm: timer: Fix several nits This changes 'Timer' to 'timer' at several places. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org>
2015-11-13 08:11:14 +00:00
Select this to enable a timer for Altera devices. Please find
nios2: convert altera timer to driver model Convert altera timer to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com>
2015-10-22 14:28:53 +00:00
details on the "Embedded Peripherals IP User Guide" of Altera.
driver: timer: Add the Atmel PIT timer driver Add the new Atmel PIT timer driver, which supports the driver model and device tree. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-08-15 09:40:26 +00:00
config ATMEL_PIT_TIMER
bool "Atmel periodic interval timer support"
depends on TIMER
help
Select this to enable a periodic interval timer for Atmel devices,
it is designed to offer maximum accuracy and efficient management,
even for systems with long response time.
timer: Add Cadence TTC timer counter support This driver was tested on Xilinx ZynqMP SoC. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-04-17 11:40:46 +00:00
config CADENCE_TTC_TIMER
bool "Cadence TTC (Triple Timer Counter)"
depends on TIMER
help
Enables support for the cadence ttc driver. This driver is present
on Xilinx Zynq and ZynqMP SoCs.
timer: dw-apb: Add Designware APB timer driver Add timer driver for the Designware APB Timer IP. This is present for example on the Altera SoCFPGA chips. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-18 13:58:32 +00:00
config DESIGNWARE_APB_TIMER
bool "Designware APB Timer"
depends on TIMER
help
Enables support for the Designware APB Timer driver. This timer is
present on Altera SoCFPGA SoCs.
sandbox: add a sandbox timer and basic test Add a sandbox timer which get time from host os and a basic test. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org>
2015-10-30 07:35:52 +00:00
config SANDBOX_TIMER
dm: timer: Fix several nits This changes 'Timer' to 'timer' at several places. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org>
2015-11-13 08:11:14 +00:00
bool "Sandbox timer support"
sandbox: add a sandbox timer and basic test Add a sandbox timer which get time from host os and a basic test. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org>
2015-10-30 07:35:52 +00:00
depends on SANDBOX && TIMER
help
Select this to enable an emulated timer for sandbox. It gets
time from host os.
x86: tsc: Move tsc_timer.c to drivers/timer To group all dm timer drivers together, move tsc timer to drivers/timer directory. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-11-13 08:11:24 +00:00
config X86_TSC_TIMER
bool "x86 Time-Stamp Counter (TSC) timer support"
depends on TIMER && X86
help
Select this to enable Time-Stamp Counter (TSC) timer for x86.
x86: tsc: Introduce config option for early timer frequency So far the TSC timer driver supports trying hardware calibration first and using device tree as last resort for its running frequency as the normal timer. However when it is used as the early timer, it only supports hardware calibration and if it fails, the driver just panics. This introduces a new config option to specify the early timer frequency in MHz and it should be equal to the value described in the device tree. Without this patch, the travis-ci testing on QEMU x86_64 target fails each time after it finishes the 'bootefi selftest' as the test.py see an error was emitted on the console like this: TSC frequency is ZERO resetting ... ### ERROR ### Please RESET the board ### It's strange that this error is consistently seen on the travis-ci machine, but only occasionally seen on my local machine (maybe 1 out of 10). Since QEMU x86_64 target enables BOOTSTAGE support which uses early timer, with this fix it should work without any failure. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-10-14 03:52:10 +00:00
config X86_TSC_TIMER_EARLY_FREQ
int "x86 TSC timer frequency in MHz when used as the early timer"
depends on X86_TSC_TIMER
default 1000
help
Sets the estimated CPU frequency in MHz when TSC is used as the
early timer and the frequency can neither be calibrated via some
hardware ways, nor got from device tree at the time when device
tree is not available yet.
drivers: timer: omap_timer: add timer driver for omap devices based on dm Adding a timer driver for omap devices based on driver model and device tree. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2015-12-24 10:38:07 +00:00
config OMAP_TIMER
bool "Omap timer support"
depends on TIMER
help
Select this to enable an timer for Omap devices.
aspeed: Add drivers common to all Aspeed SoCs Add support for Watchdog Timer, which is compatible with AST2400 and AST2500 watchdogs. There is no uclass for Watchdog yet, so the driver does not follow the driver model. It also uses fixed clock, so no clock driver is needed. Add support for timer for Aspeed ast2400/ast2500 devices. The driver actually controls several devices, but because all devices share the same Control Register, it is somewhat difficult to completely decouple them. Since only one timer is needed at the moment, this should be OK. The timer uses fixed clock, so does not rely on a clock driver. Add sysreset driver, which uses watchdog timer to do resets and particular watchdog device to use is hardcoded (0) Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-18 21:44:55 +00:00
config AST_TIMER
bool "Aspeed ast2400/ast2500 timer support"
depends on TIMER
default y if ARCH_ASPEED
help
Select this to enable timer for Aspeed ast2400/ast2500 devices.
This is a simple sys timer driver, it is compatible with lib/time.c,
but does not support any interrupts. Even though SoC has 8 hardware
counters, they are all treated as a single device by this driver.
This is mostly because they all share several registers which
makes it difficult to completely separate them.
STiH410: Add STi timer driver Add ARM global timer based timer Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-02-21 12:37:05 +00:00
config STI_TIMER
bool "STi timer support"
depends on TIMER
default y if ARCH_STI
help
Select this to enable a timer for STi devices.
drivers: timer: Introduce ARC timer driver This commit introduces timer driver for ARC. ARC timers are configured via ARC AUX registers so we use special functions to access timer control registers. This driver allows utilization of either timer0 or timer1 depending on which one is available in real hardware. Essentially only existing timers should be mentioned in board's Device Tree description. Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-03-21 11:49:47 +00:00
config ARC_TIMER
bool "ARC timer support"
depends on TIMER && ARC && CLK
help
Select this to enable built-in ARC timers.
ARC cores may have up to 2 built-in timers: timer0 and timer1,
usually at least one of them exists. Either of them is supported
in U-Boot.
nds32: Support AG101P timer DM. Support AG101P timer device tree flow. Signed-off-by: rick <rick@andestech.com>
2017-05-17 02:59:20 +00:00
config AG101P_TIMER
nds32: Support AE3XX platform. Support Andestech AE3xx platform: serial, timer device tree flow. Signed-off-by: rick <rick@andestech.com>
2017-05-18 06:37:53 +00:00
bool "AG101P timer support"
depends on TIMER && NDS32
help
Select this to enable a timer for AG01P devices.
ae3xx: timer: Rename AE3XX to ATCPIT100 ATCPIT100 is Andestech timer IP which is embeded in AE3XX and AE250 boards. So rename AE3XX to ATCPIT100 will be more make sence. Signed-off-by: rick <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-28 01:23:23 +00:00
config ATCPIT100_TIMER
bool "ATCPIT100 timer support"
atcpit100: timer: Remove arch dependency. ATCPIT100 is often used in AE3XX platform which is based on NDS32 architecture recently. But in the future Andestech will have AE250 platform which is embeded ATCPIT100 timer based on RISCV architecture. Signed-off-by: Rick Chen <rick@andestech.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-23 04:48:46 +00:00
depends on TIMER
nds32: Support AG101P timer DM. Support AG101P timer device tree flow. Signed-off-by: rick <rick@andestech.com>
2017-05-17 02:59:20 +00:00
help
ae3xx: timer: Rename AE3XX to ATCPIT100 ATCPIT100 is Andestech timer IP which is embeded in AE3XX and AE250 boards. So rename AE3XX to ATCPIT100 will be more make sence. Signed-off-by: rick <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-28 01:23:23 +00:00
Select this to enable a ATCPIT100 timer which will be embeded
in AE3XX, AE250 boards.
nds32: Support AG101P timer DM. Support AG101P timer device tree flow. Signed-off-by: rick <rick@andestech.com>
2017-05-17 02:59:20 +00:00
rockchip: timer: add device-model timer driver for RK3368 (and similar) This adds a device-model driver for the timer block in the RK3368 (and similar devices that share the same timer block, such as the RK3288) for the down-counting (i.e. non-secure) timers. This allows us to configure U-Boot for the RK3368 in such a way that we can run with the secure timer inaccessible or uninitialised (note that the ARMv8 generic timer does not count, if the secure timer is not enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 15:43:19 +00:00
config ROCKCHIP_TIMER
bool "Rockchip timer support"
depends on TIMER
help
Select this to enable support for the timer found on
Rockchip devices.
timer: stm32: Add timer support for STM32 SoCs family This timer driver is using GPT Timer (General Purpose Timer) available on all STM32 SOCs family. This driver can be used on STM32F4/F7 and H7 SoCs family Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-02-07 09:44:45 +00:00
config STM32_TIMER
bool "STM32 timer support"
depends on TIMER
help
Select this to enable support for the timer found on
STM32 devices.
timer: Add MPC83xx timer driver Add a timer driver for the MPC83xx architecture. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-08-06 08:23:38 +00:00
config MPC83XX_TIMER
bool "MPC83xx timer support"
depends on TIMER
help
Select this to enable support for the timer found on
devices based on the MPC83xx family of SoCs.
dm: implement a Timer uclass Implement a Timer uclass to work with lib/time.c. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org>
2015-10-09 05:46:34 +00:00
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