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u-boot/arch/powerpc/cpu/mpc83xx/serdes.c

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83xx: serdes setup routines This patch adds few routines to configure serdes on 837x targets. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-24 14:40:32 +00:00
/*
* Freescale SerDes initialization routine
*
Update Freescale copyrights to remove "All Rights Reserved" "All Rights Reserved" conflicts with the GPL. Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
2009-07-29 02:49:52 +00:00
* Copyright (C) 2007 Freescale Semicondutor, Inc.
mpc83xx/serdes: License cleanup: remove "All Rights Reserved" notice "All Rights Reserved" conflicts with the GPL. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2009-09-02 13:58:48 +00:00
* Copyright (C) 2008 MontaVista Software, Inc.
83xx: serdes setup routines This patch adds few routines to configure serdes on 837x targets. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-24 14:40:32 +00:00
*
* Author: Li Yang <leoli@freescale.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <config.h>
#include <common.h>
#include <asm/io.h>
ppc: Split MPC83xx SERDES code from MPC85xx/MPC86xx/QorIQ The MPC83xx SERDES control is different from the other FSL PPC chips. For now lets split it out so we can standardize on interfaces for determining of a device on SERDES is configured. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com>
2010-04-20 15:02:24 +00:00
#include <asm/fsl_mpc83xx_serdes.h>
83xx: serdes setup routines This patch adds few routines to configure serdes on 837x targets. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-24 14:40:32 +00:00
/* SerDes registers */
#define FSL_SRDSCR0_OFFS 0x0
#define FSL_SRDSCR0_DPP_1V2 0x00008800
#define FSL_SRDSCR1_OFFS 0x4
#define FSL_SRDSCR1_PLLBW 0x00000040
#define FSL_SRDSCR2_OFFS 0x8
#define FSL_SRDSCR2_VDD_1V2 0x00800000
#define FSL_SRDSCR2_SEIC_MASK 0x00001c1c
#define FSL_SRDSCR2_SEIC_SATA 0x00001414
#define FSL_SRDSCR2_SEIC_PEX 0x00001010
#define FSL_SRDSCR2_SEIC_SGMII 0x00000101
#define FSL_SRDSCR3_OFFS 0xc
#define FSL_SRDSCR3_KFR_SATA 0x10100000
#define FSL_SRDSCR3_KPH_SATA 0x04040000
#define FSL_SRDSCR3_SDFM_SATA_PEX 0x01010000
#define FSL_SRDSCR3_SDTXL_SATA 0x00000505
#define FSL_SRDSCR4_OFFS 0x10
#define FSL_SRDSCR4_PROT_SATA 0x00000808
#define FSL_SRDSCR4_PROT_PEX 0x00000101
#define FSL_SRDSCR4_PROT_SGMII 0x00000505
#define FSL_SRDSCR4_PLANE_X2 0x01000000
#define FSL_SRDSRSTCTL_OFFS 0x20
#define FSL_SRDSRSTCTL_RST 0x80000000
#define FSL_SRDSRSTCTL_SATA_RESET 0xf
mpc83xx: serdes: add forgotten shifts for rfcks The rfcks should be shifted by 28 bits left. We didn't notice the bug because we were using only 100MHz clocks (for which rfcks == 0). Though, for SGMII we'll need 125MHz clocks. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-10-02 14:31:56 +00:00
void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd)
83xx: serdes setup routines This patch adds few routines to configure serdes on 837x targets. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-24 14:40:32 +00:00
{
rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-16 13:01:15 +00:00
void *regs = (void *)CONFIG_SYS_IMMR + offset;
83xx: serdes setup routines This patch adds few routines to configure serdes on 837x targets. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-24 14:40:32 +00:00
u32 tmp;
/* 1.0V corevdd */
if (vdd) {
/* DPPE/DPPA = 0 */
tmp = in_be32(regs + FSL_SRDSCR0_OFFS);
tmp &= ~FSL_SRDSCR0_DPP_1V2;
out_be32(regs + FSL_SRDSCR0_OFFS, tmp);
/* VDD = 0 */
tmp = in_be32(regs + FSL_SRDSCR2_OFFS);
tmp &= ~FSL_SRDSCR2_VDD_1V2;
out_be32(regs + FSL_SRDSCR2_OFFS, tmp);
}
/* protocol specific configuration */
switch (proto) {
case FSL_SERDES_PROTO_SATA:
/* Set and clear reset bits */
tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS);
tmp |= FSL_SRDSRSTCTL_SATA_RESET;
out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp);
udelay(1000);
tmp &= ~FSL_SRDSRSTCTL_SATA_RESET;
out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp);
/* Configure SRDSCR1 */
tmp = in_be32(regs + FSL_SRDSCR1_OFFS);
tmp &= ~FSL_SRDSCR1_PLLBW;
out_be32(regs + FSL_SRDSCR1_OFFS, tmp);
/* Configure SRDSCR2 */
tmp = in_be32(regs + FSL_SRDSCR2_OFFS);
tmp &= ~FSL_SRDSCR2_SEIC_MASK;
tmp |= FSL_SRDSCR2_SEIC_SATA;
out_be32(regs + FSL_SRDSCR2_OFFS, tmp);
/* Configure SRDSCR3 */
tmp = FSL_SRDSCR3_KFR_SATA | FSL_SRDSCR3_KPH_SATA |
FSL_SRDSCR3_SDFM_SATA_PEX |
FSL_SRDSCR3_SDTXL_SATA;
out_be32(regs + FSL_SRDSCR3_OFFS, tmp);
/* Configure SRDSCR4 */
tmp = rfcks | FSL_SRDSCR4_PROT_SATA;
out_be32(regs + FSL_SRDSCR4_OFFS, tmp);
break;
case FSL_SERDES_PROTO_PEX:
case FSL_SERDES_PROTO_PEX_X2:
/* Configure SRDSCR1 */
tmp = in_be32(regs + FSL_SRDSCR1_OFFS);
tmp |= FSL_SRDSCR1_PLLBW;
out_be32(regs + FSL_SRDSCR1_OFFS, tmp);
/* Configure SRDSCR2 */
tmp = in_be32(regs + FSL_SRDSCR2_OFFS);
tmp &= ~FSL_SRDSCR2_SEIC_MASK;
tmp |= FSL_SRDSCR2_SEIC_PEX;
out_be32(regs + FSL_SRDSCR2_OFFS, tmp);
/* Configure SRDSCR3 */
tmp = FSL_SRDSCR3_SDFM_SATA_PEX;
out_be32(regs + FSL_SRDSCR3_OFFS, tmp);
/* Configure SRDSCR4 */
tmp = rfcks | FSL_SRDSCR4_PROT_PEX;
if (proto == FSL_SERDES_PROTO_PEX_X2)
tmp |= FSL_SRDSCR4_PLANE_X2;
out_be32(regs + FSL_SRDSCR4_OFFS, tmp);
break;
case FSL_SERDES_PROTO_SGMII:
/* Configure SRDSCR1 */
tmp = in_be32(regs + FSL_SRDSCR1_OFFS);
tmp &= ~FSL_SRDSCR1_PLLBW;
out_be32(regs + FSL_SRDSCR1_OFFS, tmp);
/* Configure SRDSCR2 */
tmp = in_be32(regs + FSL_SRDSCR2_OFFS);
tmp &= ~FSL_SRDSCR2_SEIC_MASK;
tmp |= FSL_SRDSCR2_SEIC_SGMII;
out_be32(regs + FSL_SRDSCR2_OFFS, tmp);
/* Configure SRDSCR3 */
out_be32(regs + FSL_SRDSCR3_OFFS, 0);
/* Configure SRDSCR4 */
tmp = rfcks | FSL_SRDSCR4_PROT_SGMII;
out_be32(regs + FSL_SRDSCR4_OFFS, tmp);
break;
default:
return;
}
/* Do a software reset */
tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS);
tmp |= FSL_SRDSRSTCTL_RST;
out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp);
}
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