2018-05-06 21:58:06 +00:00
|
|
|
// SPDX-License-Identifier: GPL-2.0+
|
2015-01-15 09:01:51 +00:00
|
|
|
/*
|
|
|
|
* (C) Copyright 2014 - 2015 Xilinx, Inc.
|
2023-07-10 12:35:49 +00:00
|
|
|
* Michal Simek <michal.simek@amd.com>
|
2015-01-15 09:01:51 +00:00
|
|
|
*/
|
|
|
|
|
|
|
|
#include <common.h>
|
2020-05-10 17:40:02 +00:00
|
|
|
#include <init.h>
|
2019-12-28 17:44:59 +00:00
|
|
|
#include <time.h>
|
2015-04-15 12:59:19 +00:00
|
|
|
#include <asm/arch/clk.h>
|
2015-01-15 09:01:51 +00:00
|
|
|
#include <asm/arch/hardware.h>
|
|
|
|
#include <asm/arch/sys_proto.h>
|
2020-10-31 03:38:53 +00:00
|
|
|
#include <asm/global_data.h>
|
2015-01-15 09:01:51 +00:00
|
|
|
|
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
|
2015-11-05 07:34:35 +00:00
|
|
|
unsigned long zynqmp_get_system_timer_freq(void)
|
|
|
|
{
|
|
|
|
u32 ver = zynqmp_get_silicon_version();
|
|
|
|
|
|
|
|
switch (ver) {
|
|
|
|
case ZYNQMP_CSU_VERSION_QEMU:
|
|
|
|
return 50000000;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 100000000;
|
|
|
|
}
|
|
|
|
|
2015-01-15 09:01:51 +00:00
|
|
|
#ifdef CONFIG_CLOCKS
|
|
|
|
/**
|
|
|
|
* set_cpu_clk_info() - Initialize clock framework
|
|
|
|
* Always returns zero.
|
|
|
|
*
|
|
|
|
* This function is called from common code after relocation and sets up the
|
|
|
|
* clock framework. The framework must not be used before this function had been
|
|
|
|
* called.
|
|
|
|
*/
|
|
|
|
int set_cpu_clk_info(void)
|
|
|
|
{
|
|
|
|
gd->cpu_clk = get_tbclk();
|
|
|
|
|
2018-05-14 13:33:22 +00:00
|
|
|
gd->bd->bi_arm_freq = gd->cpu_clk / 1000000;
|
2015-01-15 09:01:51 +00:00
|
|
|
|
|
|
|
gd->bd->bi_dsp_freq = 0;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif
|