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u-boot/arch/riscv/Kconfig

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riscv: kconfig: Normalize architecture name spelling It's RISC-V that is the official name, not RISCV. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
2018-09-26 13:55:06 +00:00
menu "RISC-V architecture"
riscv: Add Kconfig to support RISC-V Add Kconfig and makefile for RISC-V Also modify MAINTAINERS for it. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2017-12-26 05:55:52 +00:00
depends on RISCV
config SYS_ARCH
default "riscv"
choice
prompt "Target select"
optional
riscv: cpu: nx25: Rename as ax25 Andes has rearranged the product combinations. nx25 and ax25 both are RISC-V architecture cpu core. But ax25 has MMU unit inside, and nx25 is not. Cpu nx25 and platform ae250 are arranged in pairs. Cpu ax25 and platform ae350 are arranged in pairs. This patch will rename nx25 as ax25 ae250 as ae350 nx25-ae250 as ax25-ae350 including filename, variable, string and definition. Then u-boot can boot linux kernel in ae350 platform reasonably. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Cc: Greentime Hu <green.hu@gmail.com>
2018-05-29 01:54:40 +00:00
config TARGET_AX25_AE350
bool "Support ax25-ae350"
riscv: Add Kconfig to support RISC-V Add Kconfig and makefile for RISC-V Also modify MAINTAINERS for it. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2017-12-26 05:55:52 +00:00
riscv: Add QEMU virt board support This adds QEMU RISC-V 'virt' board target support, with the hope of helping people easily test U-Boot on RISC-V. The QEMU virt machine models a generic RISC-V virtual machine with support for the VirtIO standard networking and block storage devices. It has CLINT, PLIC, 16550A UART devices in addition to VirtIO and it also uses device-tree to pass configuration information to guest software. It implements RISC-V privileged architecture spec v1.10. Both 32-bit and 64-bit builds are supported. Support is pretty much preliminary, only booting to U-Boot shell with the UART driver on a single core. Booting Linux is not supported yet. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-09-26 13:55:21 +00:00
config TARGET_QEMU_VIRT
bool "Support QEMU Virt Board"
riscv: Add SiFive FU540 board support This patch adds SiFive FU540 board support. For now, only SiFive serial, SiFive PRCI, and Cadance MACB drivers are only enabled. The SiFive FU540 defconfig by default builds U-Boot for S-Mode because U-Boot on SiFive FU540 will run in S-Mode as payload of BBL or OpenSBI. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-25 08:15:19 +00:00
config TARGET_SIFIVE_FU540
bool "Support SiFive FU540 Board"
riscv: Add Kconfig to support RISC-V Add Kconfig and makefile for RISC-V Also modify MAINTAINERS for it. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2017-12-26 05:55:52 +00:00
endchoice
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
2018-11-07 01:34:06 +00:00
# board-specific options below
riscv: cpu: nx25: Rename as ax25 Andes has rearranged the product combinations. nx25 and ax25 both are RISC-V architecture cpu core. But ax25 has MMU unit inside, and nx25 is not. Cpu nx25 and platform ae250 are arranged in pairs. Cpu ax25 and platform ae350 are arranged in pairs. This patch will rename nx25 as ax25 ae250 as ae350 nx25-ae250 as ax25-ae350 including filename, variable, string and definition. Then u-boot can boot linux kernel in ae350 platform reasonably. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Cc: Greentime Hu <green.hu@gmail.com>
2018-05-29 01:54:40 +00:00
source "board/AndesTech/ax25-ae350/Kconfig"
riscv: Add QEMU virt board support This adds QEMU RISC-V 'virt' board target support, with the hope of helping people easily test U-Boot on RISC-V. The QEMU virt machine models a generic RISC-V virtual machine with support for the VirtIO standard networking and block storage devices. It has CLINT, PLIC, 16550A UART devices in addition to VirtIO and it also uses device-tree to pass configuration information to guest software. It implements RISC-V privileged architecture spec v1.10. Both 32-bit and 64-bit builds are supported. Support is pretty much preliminary, only booting to U-Boot shell with the UART driver on a single core. Booting Linux is not supported yet. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-09-26 13:55:21 +00:00
source "board/emulation/qemu-riscv/Kconfig"
riscv: Add SiFive FU540 board support This patch adds SiFive FU540 board support. For now, only SiFive serial, SiFive PRCI, and Cadance MACB drivers are only enabled. The SiFive FU540 defconfig by default builds U-Boot for S-Mode because U-Boot on SiFive FU540 will run in S-Mode as payload of BBL or OpenSBI. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-25 08:15:19 +00:00
source "board/sifive/fu540/Kconfig"
riscv: Add Kconfig to support RISC-V Add Kconfig and makefile for RISC-V Also modify MAINTAINERS for it. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2017-12-26 05:55:52 +00:00
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
2018-11-07 01:34:06 +00:00
# platform-specific options below
source "arch/riscv/cpu/ax25/Kconfig"
riscv: Rename cpu/qemu to cpu/generic The QEMU CPU support under arch/riscv is pretty much generic and works fine for SiFive Unleashed as well. In fact, there will be quite a few RISC-V SOCs for which QEMU CPU support will work fine. This patch renames cpu/qemu to cpu/generic to indicate the above fact. If there are SOC specific errata workarounds required in cpu/generic then those can be done at runtime in cpu/generic based on CPU vendor specific DT compatible string. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-25 08:14:10 +00:00
source "arch/riscv/cpu/generic/Kconfig"
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
2018-11-07 01:34:06 +00:00
# architecture-specific options below
riscv: Add Kconfig to support RISC-V Add Kconfig and makefile for RISC-V Also modify MAINTAINERS for it. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2017-12-26 05:55:52 +00:00
choice
riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I RISC-V defines the base integer instruction sets as RV32I and RV64I. Rename CPU_RISCV_32 and CPU_RISCV_64 to ARCH_RV32I and ARCH_RV64I to match this convention. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-22 10:26:12 +00:00
prompt "Base ISA"
default ARCH_RV32I
riscv: Add Kconfig to support RISC-V Add Kconfig and makefile for RISC-V Also modify MAINTAINERS for it. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2017-12-26 05:55:52 +00:00
riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I RISC-V defines the base integer instruction sets as RV32I and RV64I. Rename CPU_RISCV_32 and CPU_RISCV_64 to ARCH_RV32I and ARCH_RV64I to match this convention. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-22 10:26:12 +00:00
config ARCH_RV32I
bool "RV32I"
riscv: Add Kconfig to support RISC-V Add Kconfig and makefile for RISC-V Also modify MAINTAINERS for it. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2017-12-26 05:55:52 +00:00
select 32BIT
help
riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I RISC-V defines the base integer instruction sets as RV32I and RV64I. Rename CPU_RISCV_32 and CPU_RISCV_64 to ARCH_RV32I and ARCH_RV64I to match this convention. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-22 10:26:12 +00:00
Choose this option to target the RV32I base integer instruction set.
riscv: Add Kconfig to support RISC-V Add Kconfig and makefile for RISC-V Also modify MAINTAINERS for it. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2017-12-26 05:55:52 +00:00
riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I RISC-V defines the base integer instruction sets as RV32I and RV64I. Rename CPU_RISCV_32 and CPU_RISCV_64 to ARCH_RV32I and ARCH_RV64I to match this convention. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-22 10:26:12 +00:00
config ARCH_RV64I
bool "RV64I"
riscv: Add Kconfig to support RISC-V Add Kconfig and makefile for RISC-V Also modify MAINTAINERS for it. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2017-12-26 05:55:52 +00:00
select 64BIT
riscv: select CONFIG_PHYS_64BIT on RV64I systems CONFIG_PHYS_64BIT should be enabled on RV64I systems. Select it. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-22 10:26:13 +00:00
select PHYS_64BIT
riscv: Add Kconfig to support RISC-V Add Kconfig and makefile for RISC-V Also modify MAINTAINERS for it. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2017-12-26 05:55:52 +00:00
help
riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I RISC-V defines the base integer instruction sets as RV32I and RV64I. Rename CPU_RISCV_32 and CPU_RISCV_64 to ARCH_RV32I and ARCH_RV64I to match this convention. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-22 10:26:12 +00:00
Choose this option to target the RV64I base integer instruction set.
riscv: Add Kconfig to support RISC-V Add Kconfig and makefile for RISC-V Also modify MAINTAINERS for it. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2017-12-26 05:55:52 +00:00
endchoice
riscv: add Kconfig entries for the code model RISC-V has two code models, medium low (medlow) and medium any (medany). Medlow limits addressable memory to a single 2 GiB range between the absolute addresses -2 GiB and +2 GiB. Medany limits addressable memory to any single 2 GiB address range. By default, medlow is selected for U-Boot on both 32-bit and 64-bit systems. The -mcmodel compiler flag is selected according to the Kconfig configuration. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> [bmeng: adjust to make medlow the default code model for U-Boot] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-12 14:12:23 +00:00
choice
prompt "Code Model"
default CMODEL_MEDLOW
config CMODEL_MEDLOW
bool "medium low code model"
help
U-Boot and its statically defined symbols must lie within a single 2 GiB
address range and must lie between absolute addresses -2 GiB and +2 GiB.
config CMODEL_MEDANY
bool "medium any code model"
help
U-Boot and its statically defined symbols must be within any single 2 GiB
address range.
endchoice
riscv: Introduce a Kconfig option for machine mode So far we have a Kconfig option for supervisor mode. This adds an option for the machine mode. Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-12-12 14:12:29 +00:00
choice
prompt "Run Mode"
default RISCV_MMODE
config RISCV_MMODE
bool "Machine"
help
Choose this option to build U-Boot for RISC-V M-Mode.
config RISCV_SMODE
bool "Supervisor"
help
Choose this option to build U-Boot for RISC-V S-Mode.
endchoice
riscv: add Kconfig entries for the C and A ISA extensions Add Kconfig entries for the C (compressed instructions) and A (atomic instructions) ISA extensions. Only the C ISA extension is selectable. This matches the configuration in Linux. The Kconfig entries are not used yet. A follow-up patch will select the appropriate compiler flags based on the Kconfig configuration. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-11-22 10:26:14 +00:00
config RISCV_ISA_C
bool "Emit compressed instructions"
default y
help
Adds "C" to the ISA subsets that the toolchain is allowed to emit
when building U-Boot, which results in compressed instructions in the
U-Boot binary.
config RISCV_ISA_A
def_bool y
riscv: Add Kconfig to support RISC-V Add Kconfig and makefile for RISC-V Also modify MAINTAINERS for it. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2017-12-26 05:55:52 +00:00
config 32BIT
bool
config 64BIT
bool
riscv: Add a SYSCON driver for SiFive's Core Local Interruptor This adds U-Boot syscon driver for SiFive's Core Local Interruptor (CLINT). The CLINT block holds memory-mapped control and status registers associated with software and timer interrupts. This driver implements the riscv_get_time() API as required by the generic RISC-V timer driver, as well as some other APIs that are needed for handling IPI. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-12 14:12:30 +00:00
config SIFIVE_CLINT
bool
depends on RISCV_MMODE
select REGMAP
select SYSCON
help
The SiFive CLINT block holds memory-mapped control and status registers
associated with software and timer interrupts.
riscv: Implement riscv_get_time() API using rdtime instruction This adds an implementation of riscv_get_time() API that is using rdtime instruction. This is the case for S-mode U-Boot, and is useful for processors that support rdtime in M-mode too. Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-12-12 14:12:31 +00:00
config RISCV_RDTIME
bool
default y if RISCV_SMODE
help
The provides the riscv_get_time() API that is implemented using the
standard rdtime instruction. This is the case for S-mode U-Boot, and
is useful for processors that support rdtime in M-mode too.
riscv: Enlarge the default SYS_MALLOC_F_LEN Increase the heap size for the pre-relocation stage, so that CPU driver can be loaded. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-12 14:12:33 +00:00
config SYS_MALLOC_F_LEN
default 0x1000
riscv: Add Kconfig to support RISC-V Add Kconfig and makefile for RISC-V Also modify MAINTAINERS for it. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2017-12-26 05:55:52 +00:00
endmenu
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