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u-boot/arch/mips/cpu/mips32/start.S

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* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
/*
* Startup Code for MIPS32 CPU-core
*
* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
Replace CONFIG_SYS_GBL_DATA_SIZE by auto-generated value CONFIG_SYS_GBL_DATA_SIZE has always been just a bad workarond for not being able to use "sizeof(struct global_data)" in assembler files. Recent experience has shown that manual synchronization is not reliable enough. This patch renames CONFIG_SYS_GBL_DATA_SIZE into GENERATED_GBL_DATA_SIZE which gets automatically generated by the asm-offsets tool. In the result, all definitions of this value can be deleted from the board config files. We have to make sure that all files that reference such data include the new <asm-offsets.h> file. No other changes have been done yet, but it is obvious that similar changes / simplifications can be done for other, related macro definitions as well. Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: Kumar Gala <galak@kernel.crashing.org>
2010-10-26 12:34:52 +00:00
#include <asm-offsets.h>
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
#include <config.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
MIPS: make cache operation mode configurable Currently the cache operation mode is hard-coded to CONF_CM_CACHABLE_NONCOHERENT. This is not appropiate for CPUs or SOCs which operate at a different mode. This patch makes the cache operation mode configurable via board config. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Acked-by: Thomas Langer <thomas.langer@lantiq.com> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-07-27 11:22:38 +00:00
#ifndef CONFIG_SYS_MIPS_CACHE_MODE
#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
#endif
[MIPS] Cleanup CP0 Status initialization Add setup_c0_status from Linux. For the moment we disable interrupts, set CU0, mark the kernel mode, and clear ERL and EXL. This is good enough for reset-time configuration and will work well across most processors. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2008-03-25 12:30:07 +00:00
/*
* For the moment disable interrupts, mark the kernel mode and
* set ST0_KX so that the CPU does not spit fire when using
* 64-bit addresses.
*/
.macro setup_c0_status set clr
.set push
mfc0 t0, CP0_STATUS
or t0, ST0_CU0 | \set | 0x1f | \clr
xor t0, 0x1f | \clr
mtc0 t0, CP0_STATUS
.set noreorder
sll zero, 3 # ehb
.set pop
.endm
.macro setup_c0_status_reset
#ifdef CONFIG_64BIT
setup_c0_status ST0_KX 0
#else
setup_c0_status 0 0
#endif
.endm
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
#define RVECENT(f,n) \
b f; nop
#define XVECENT(f,bev) \
b f ; \
li k0,bev
.set noreorder
.globl _start
.text
_start:
MIPS: Coding style cleanups on common assembly files Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-06 15:18:13 +00:00
RVECENT(reset,0) # U-boot entry point
RVECENT(reset,1) # software reboot
MIPS: rename INFINEON_EBU_BOOTCFG to CONFIG_SYS_XWAY_EBU_BOOTFG This define is a board-specific config option and should be renamed to follow the U-Boot naming convention. Additionally, add an explaining comment for this option. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Acked-by: Thomas Langer <thomas.langer@lantiq.com> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-07-27 11:22:37 +00:00
#ifdef CONFIG_SYS_XWAY_EBU_BOOTCFG
/*
* Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
* access external NOR flashes. If the board boots from NOR flash the
* internal BootROM does a blind read at address 0xB0000010 to read the
* initial configuration for that EBU in order to access the flash
* device with correct parameters. This config option is board-specific.
*/
.word CONFIG_SYS_XWAY_EBU_BOOTCFG
.word 0x00000000
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
#else
RVECENT(romReserved,2)
#endif
RVECENT(romReserved,3)
RVECENT(romReserved,4)
RVECENT(romReserved,5)
RVECENT(romReserved,6)
RVECENT(romReserved,7)
RVECENT(romReserved,8)
RVECENT(romReserved,9)
RVECENT(romReserved,10)
RVECENT(romReserved,11)
RVECENT(romReserved,12)
RVECENT(romReserved,13)
RVECENT(romReserved,14)
RVECENT(romReserved,15)
RVECENT(romReserved,16)
* Code cleanup: - remove trailing white space, trailing empty lines, C++ comments, etc. - split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c) * Patches by Kenneth Johansson, 25 Jun 2003: - major rework of command structure (work done mostly by Michal Cendrowski and Joakim Kristiansen)
2003-06-27 21:31:46 +00:00
RVECENT(romReserved,17)
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
RVECENT(romReserved,18)
RVECENT(romReserved,19)
RVECENT(romReserved,20)
RVECENT(romReserved,21)
RVECENT(romReserved,22)
RVECENT(romReserved,23)
RVECENT(romReserved,24)
RVECENT(romReserved,25)
RVECENT(romReserved,26)
RVECENT(romReserved,27)
RVECENT(romReserved,28)
RVECENT(romReserved,29)
RVECENT(romReserved,30)
RVECENT(romReserved,31)
RVECENT(romReserved,32)
RVECENT(romReserved,33)
RVECENT(romReserved,34)
RVECENT(romReserved,35)
RVECENT(romReserved,36)
RVECENT(romReserved,37)
RVECENT(romReserved,38)
RVECENT(romReserved,39)
RVECENT(romReserved,40)
RVECENT(romReserved,41)
RVECENT(romReserved,42)
RVECENT(romReserved,43)
RVECENT(romReserved,44)
RVECENT(romReserved,45)
RVECENT(romReserved,46)
RVECENT(romReserved,47)
RVECENT(romReserved,48)
RVECENT(romReserved,49)
RVECENT(romReserved,50)
RVECENT(romReserved,51)
RVECENT(romReserved,52)
RVECENT(romReserved,53)
RVECENT(romReserved,54)
RVECENT(romReserved,55)
RVECENT(romReserved,56)
RVECENT(romReserved,57)
RVECENT(romReserved,58)
RVECENT(romReserved,59)
RVECENT(romReserved,60)
RVECENT(romReserved,61)
RVECENT(romReserved,62)
* Code cleanup: - remove trailing white space, trailing empty lines, C++ comments, etc. - split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c) * Patches by Kenneth Johansson, 25 Jun 2003: - major rework of command structure (work done mostly by Michal Cendrowski and Joakim Kristiansen)
2003-06-27 21:31:46 +00:00
RVECENT(romReserved,63)
MIPS: Coding style cleanups on common assembly files Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-06 15:18:13 +00:00
XVECENT(romExcHandle,0x200) # bfc00200: R4000 tlbmiss vector
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
RVECENT(romReserved,65)
RVECENT(romReserved,66)
RVECENT(romReserved,67)
RVECENT(romReserved,68)
RVECENT(romReserved,69)
RVECENT(romReserved,70)
RVECENT(romReserved,71)
RVECENT(romReserved,72)
RVECENT(romReserved,73)
RVECENT(romReserved,74)
RVECENT(romReserved,75)
RVECENT(romReserved,76)
RVECENT(romReserved,77)
RVECENT(romReserved,78)
* Code cleanup: - remove trailing white space, trailing empty lines, C++ comments, etc. - split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c) * Patches by Kenneth Johansson, 25 Jun 2003: - major rework of command structure (work done mostly by Michal Cendrowski and Joakim Kristiansen)
2003-06-27 21:31:46 +00:00
RVECENT(romReserved,79)
MIPS: Coding style cleanups on common assembly files Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-06 15:18:13 +00:00
XVECENT(romExcHandle,0x280) # bfc00280: R4000 xtlbmiss vector
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
RVECENT(romReserved,81)
RVECENT(romReserved,82)
RVECENT(romReserved,83)
RVECENT(romReserved,84)
RVECENT(romReserved,85)
RVECENT(romReserved,86)
RVECENT(romReserved,87)
RVECENT(romReserved,88)
RVECENT(romReserved,89)
RVECENT(romReserved,90)
RVECENT(romReserved,91)
RVECENT(romReserved,92)
RVECENT(romReserved,93)
RVECENT(romReserved,94)
* Code cleanup: - remove trailing white space, trailing empty lines, C++ comments, etc. - split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c) * Patches by Kenneth Johansson, 25 Jun 2003: - major rework of command structure (work done mostly by Michal Cendrowski and Joakim Kristiansen)
2003-06-27 21:31:46 +00:00
RVECENT(romReserved,95)
MIPS: Coding style cleanups on common assembly files Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-06 15:18:13 +00:00
XVECENT(romExcHandle,0x300) # bfc00300: R4000 cache vector
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
RVECENT(romReserved,97)
RVECENT(romReserved,98)
RVECENT(romReserved,99)
RVECENT(romReserved,100)
RVECENT(romReserved,101)
RVECENT(romReserved,102)
RVECENT(romReserved,103)
RVECENT(romReserved,104)
RVECENT(romReserved,105)
RVECENT(romReserved,106)
RVECENT(romReserved,107)
RVECENT(romReserved,108)
RVECENT(romReserved,109)
RVECENT(romReserved,110)
RVECENT(romReserved,111)
MIPS: Coding style cleanups on common assembly files Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-06 15:18:13 +00:00
XVECENT(romExcHandle,0x380) # bfc00380: R4000 general vector
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
RVECENT(romReserved,113)
RVECENT(romReserved,114)
RVECENT(romReserved,115)
RVECENT(romReserved,116)
RVECENT(romReserved,116)
RVECENT(romReserved,118)
RVECENT(romReserved,119)
RVECENT(romReserved,120)
RVECENT(romReserved,121)
RVECENT(romReserved,122)
RVECENT(romReserved,123)
RVECENT(romReserved,124)
RVECENT(romReserved,125)
RVECENT(romReserved,126)
RVECENT(romReserved,127)
* Code cleanup: - remove trailing white space, trailing empty lines, C++ comments, etc. - split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c) * Patches by Kenneth Johansson, 25 Jun 2003: - major rework of command structure (work done mostly by Michal Cendrowski and Joakim Kristiansen)
2003-06-27 21:31:46 +00:00
MIPS: Coding style cleanups on common assembly files Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-06 15:18:13 +00:00
/*
* We hope there are no more reserved vectors!
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
* 128 * 8 == 1024 == 0x400
* so this is address R_VEC+0x400 == 0xbfc00400
*/
.align 4
reset:
MIPS: Coding style cleanups on common assembly files Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-06 15:18:13 +00:00
/* Clear watch registers */
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
mtc0 zero, CP0_WATCHLO
mtc0 zero, CP0_WATCHHI
MIPS: Coding style cleanups on common assembly files Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-06 15:18:13 +00:00
/* WP(Watch Pending), SW0/1 should be cleared */
[MIPS] Initialize CP0 Cause before setting up CP0 Status register Without this change, we'll be suffering from deffered WATCH exception once Status.EXL is cleared. Make sure Cause.WP is cleared. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2008-03-25 12:30:07 +00:00
mtc0 zero, CP0_CAUSE
[MIPS] Cleanup CP0 Status initialization Add setup_c0_status from Linux. For the moment we disable interrupts, set CU0, mark the kernel mode, and clear ERL and EXL. This is good enough for reset-time configuration and will work well across most processors. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2008-03-25 12:30:07 +00:00
setup_c0_status_reset
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
/* Init Timer */
mtc0 zero, CP0_COUNT
mtc0 zero, CP0_COMPARE
MIPS: Coding style cleanups on common assembly files Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-06 15:18:13 +00:00
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
/* CONFIG0 register */
li t0, CONF_CM_UNCACHED
mtc0 t0, CP0_CONFIG
MIPS: Coding style cleanups on common assembly files Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-06 15:18:13 +00:00
#endif
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
MIPS: Coding style cleanups on common assembly files Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-06 15:18:13 +00:00
/* Initialize $gp */
[MIPS] MIPS 4K core: Coding style cleanups No logical changes. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2007-10-27 06:27:06 +00:00
bal 1f
MIPS: Coding style cleanups on common assembly files Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-06 15:18:13 +00:00
nop
[MIPS] Fix $gp usage Now we load $gp with _GLOBAL_OFFSET_TABLE_, but this is incorrect use. As a general principle, we should use _gp for $gp. Thanks to linker script's help we fortunately have _gp which equals to _GLOBAL_OFFSET_TABLE_. But once _gp gets out of alignment, we will not be able to access to GOT entires, global variables and procedure entry points. The right thing to do is to use _gp. This patch also introduce a new symbol `.gpword _GLOBAL_OFFSET_TABLE_' which holds the offset from _gp. When updating GOT entries, we use this offset and _gp to calculate the final _GLOBAL_OFFSET_TABLE_. This patch is originally submitted by Vlad Lungu <vlad@comsys.ro>, then I made some change to leave over num_got_entries. Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com> Cc: Vlad Lungu <vlad@comsys.ro>
2007-10-21 01:55:36 +00:00
.word _gp
[MIPS] MIPS 4K core: Coding style cleanups No logical changes. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2007-10-27 06:27:06 +00:00
1:
[MIPS] Remove useless instructions for initializing $gp. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2007-11-17 11:05:26 +00:00
lw gp, 0(ra)
Fix U-Boot compilation for MIPS boards using ELDK 4.0
2005-12-01 01:15:07 +00:00
MIPS: Coding style cleanups on common assembly files Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-06 15:18:13 +00:00
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
/* Initialize any external memory */
[MIPS] MIPS 4K core: Coding style cleanups No logical changes. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2007-10-27 06:27:06 +00:00
la t9, lowlevel_init
jalr t9
MIPS: Coding style cleanups on common assembly files Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-06 15:18:13 +00:00
nop
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
MIPS: Coding style cleanups on common assembly files Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-06 15:18:13 +00:00
/* Initialize caches... */
[MIPS] MIPS 4K core: Coding style cleanups No logical changes. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2007-10-27 06:27:06 +00:00
la t9, mips_cache_reset
jalr t9
MIPS: Coding style cleanups on common assembly files Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-06 15:18:13 +00:00
nop
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
MIPS: Coding style cleanups on common assembly files Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-06 15:18:13 +00:00
/* ... and enable them */
MIPS: make cache operation mode configurable Currently the cache operation mode is hard-coded to CONF_CM_CACHABLE_NONCOHERENT. This is not appropiate for CPUs or SOCs which operate at a different mode. This patch makes the cache operation mode configurable via board config. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Acked-by: Thomas Langer <thomas.langer@lantiq.com> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-07-27 11:22:38 +00:00
li t0, CONFIG_SYS_MIPS_CACHE_MODE
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
mtc0 t0, CP0_CONFIG
MIPS: Coding style cleanups on common assembly files Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-06 15:18:13 +00:00
#endif
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
MIPS: Coding style cleanups on common assembly files Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-06 15:18:13 +00:00
/* Set up temporary stack */
MIPS: start.S: set sp register directly The current code uses two instructions to load the stack pointer into the 'sp' register. This results in the following assembly code: 468: 3c088040 lui t0,0x8040 46c: 251d0000 addiu sp,t0,0 The first instuction loads the stack pointer into the 't0' register then the value of the 'sp' register is computed by adding zero to the value of the 't0' register. The same issue present on the 64-bit version as well: 56c: 3c0c8040 lui t0,0x8040 570: 659d0000 daddiu sp,t0,0 Change the code to load the stack pointer directly into the 'sp' register. The generated code is functionally equivalent to the previous version but it is simpler. 32-bit: 468: 3c1d8040 lui sp,0x8040 64-bit: 56c: 3c1d8040 lui sp,0x8040 Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-24 06:27:52 +00:00
li sp, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
la t9, board_init_f
Use jr as register jump instruction Current assembler codes are inconsistent in the way of register jump instruction usage; some use jr, some use j. Of course GNU as allows both usages, but as can be expected from `Jump Register' the mnemonic `jr' is more intuitive than `j'. For example, Linux doesn't have `j <reg>' usage at all. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2008-04-17 14:35:13 +00:00
jr t9
MIPS: Coding style cleanups on common assembly files Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-06 15:18:13 +00:00
nop
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
*
* a0 = addr_sp
* a1 = gd
* a2 = destination address
*/
.globl relocate_code
.ent relocate_code
relocate_code:
MIPS: Coding style cleanups on common assembly files Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-06 15:18:13 +00:00
move sp, a0 # set new stack pointer
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
MIPS: start.S: save reused arguments earlier in relocate_code Save the reused parameters at the beginning of the 'relocate_code' function. This makes the function a bit more readable. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-24 06:27:53 +00:00
move s0, a1 # save gd in s0
move s2, a2 # save destination address in s2
rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-16 13:01:15 +00:00
li t0, CONFIG_SYS_MONITOR_BASE
MIPS: start.S: simplify relocation offset calculation The current code uses four instructions and a temporary register to calculate the relocation offset and to adjust the gp register. The relocation offset can be calculated directly from the CONFIG_SYS_MONITOR_BASE constant and from the destination address. The resulting offset can be used to adjust the gp pointer. This approach makes the code a bit simpler because it needs two instructions only. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-24 06:27:54 +00:00
sub s1, s2, t0 # s1 <-- relocation offset
* Implement new mechanism to export U-Boot's functions to standalone applications: instead of using (PPC-specific) system calls we now use a jump table; please see doc/README.standalone for details * Patch by Dave Westwood, 24 Jul 2003: added support for Unity OS (a proprietary OS)
2003-07-24 23:38:38 +00:00
la t3, in_ram
MIPS: Coding style cleanups on common assembly files Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-06 15:18:13 +00:00
lw t2, -12(t3) # t2 <-- uboot_end_data
* Implement new mechanism to export U-Boot's functions to standalone applications: instead of using (PPC-specific) system calls we now use a jump table; please see doc/README.standalone for details * Patch by Dave Westwood, 24 Jul 2003: added support for Unity OS (a proprietary OS)
2003-07-24 23:38:38 +00:00
move t1, a2
MIPS: start.S: simplify relocation offset calculation The current code uses four instructions and a temporary register to calculate the relocation offset and to adjust the gp register. The relocation offset can be calculated directly from the CONFIG_SYS_MONITOR_BASE constant and from the destination address. The resulting offset can be used to adjust the gp pointer. This approach makes the code a bit simpler because it needs two instructions only. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-24 06:27:54 +00:00
add gp, s1 # adjust gp
* Code cleanup: - remove trailing white space, trailing empty lines, C++ comments, etc. - split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c) * Patches by Kenneth Johansson, 25 Jun 2003: - major rework of command structure (work done mostly by Michal Cendrowski and Joakim Kristiansen)
2003-06-27 21:31:46 +00:00
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
/*
* t0 = source address
* t1 = target address
* t2 = source end address
*/
1:
lw t3, 0(t0)
sw t3, 0(t1)
addu t0, 4
MIPS: start.S: fix boundary check in relocate_code The loop code copies more data with one than necessary due to the 'ble' instuction. Use the 'blt' instruction instead to fix that. Due to the lack of suitable hardware the Xburst specific code is compile tested only. However the change is quite obvious. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-24 06:27:51 +00:00
blt t0, t2, 1b
MIPS: Coding style cleanups on common assembly files Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-06 15:18:13 +00:00
addu t1, 4
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
MIPS: Coding style cleanups on common assembly files Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-06 15:18:13 +00:00
/* If caches were enabled, we would have to flush them here. */
MIPS: start.S: don't save flush_cache parameters in advance Saving the parameters in advance unnecessarily complicates the code. The destination address is already saved in the 's2' register, and that register is not clobbered by the copy loop. The size of the copied data can be computed after the copy loop is done. Change the code to compute the size parameter right before calling flush_cache, and set the destination address parameter in the delay slot of the actuall call. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-24 06:27:55 +00:00
sub a1, t1, s2 # a1 <-- size
MIPS: Flush data cache upon relocation This patch now adds a flush to the data cache upon relocation. The current implementation is missing this. Only a comment states that it should be done. So let's really do it now. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2008-11-18 15:36:12 +00:00
la t9, flush_cache
jalr t9
MIPS: start.S: don't save flush_cache parameters in advance Saving the parameters in advance unnecessarily complicates the code. The destination address is already saved in the 's2' register, and that register is not clobbered by the copy loop. The size of the copied data can be computed after the copy loop is done. Change the code to compute the size parameter right before calling flush_cache, and set the destination address parameter in the delay slot of the actuall call. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-24 06:27:55 +00:00
move a0, s2 # a0 <-- destination address
MIPS: Flush data cache upon relocation This patch now adds a flush to the data cache upon relocation. The current implementation is missing this. Only a comment states that it should be done. So let's really do it now. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2008-11-18 15:36:12 +00:00
MIPS: Coding style cleanups on common assembly files Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-06 15:18:13 +00:00
/* Jump to where we've relocated ourselves */
MIPS: Flush data cache upon relocation This patch now adds a flush to the data cache upon relocation. The current implementation is missing this. Only a comment states that it should be done. So let's really do it now. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2008-11-18 15:36:12 +00:00
addi t0, s2, in_ram - _start
Use jr as register jump instruction Current assembler codes are inconsistent in the way of register jump instruction usage; some use jr, some use j. Of course GNU as allows both usages, but as can be expected from `Jump Register' the mnemonic `jr' is more intuitive than `j'. For example, Linux doesn't have `j <reg>' usage at all. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2008-04-17 14:35:13 +00:00
jr t0
MIPS: Coding style cleanups on common assembly files Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-06 15:18:13 +00:00
nop
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
Big white-space cleanup. This commit gets rid of a huge amount of silly white-space issues. Especially, all sequences of SPACEs followed by TAB characters get removed (unless they appear in print statements). Also remove all embedded "vim:" and "vi:" statements which hide indentation problems. Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-05-20 14:00:29 +00:00
.word _gp
Allow building mips versions with ELDK 3.1.1 .gpword works only with local symbols on certain binutils versions Signed-off-by: Vlad Lungu <vlad.lungu@windrvier.com>
2008-05-05 11:04:00 +00:00
.word _GLOBAL_OFFSET_TABLE_
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
.word uboot_end_data
.word uboot_end
.word num_got_entries
in_ram:
[MIPS] Fix $gp usage Now we load $gp with _GLOBAL_OFFSET_TABLE_, but this is incorrect use. As a general principle, we should use _gp for $gp. Thanks to linker script's help we fortunately have _gp which equals to _GLOBAL_OFFSET_TABLE_. But once _gp gets out of alignment, we will not be able to access to GOT entires, global variables and procedure entry points. The right thing to do is to use _gp. This patch also introduce a new symbol `.gpword _GLOBAL_OFFSET_TABLE_' which holds the offset from _gp. When updating GOT entries, we use this offset and _gp to calculate the final _GLOBAL_OFFSET_TABLE_. This patch is originally submitted by Vlad Lungu <vlad@comsys.ro>, then I made some change to leave over num_got_entries. Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com> Cc: Vlad Lungu <vlad@comsys.ro>
2007-10-21 01:55:36 +00:00
/*
* Now we want to update GOT.
*
* GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
* generated by GNU ld. Skip these reserved entries from relocation.
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
*/
MIPS: Coding style cleanups on common assembly files Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-06 15:18:13 +00:00
lw t3, -4(t0) # t3 <-- num_got_entries
lw t4, -16(t0) # t4 <-- _GLOBAL_OFFSET_TABLE_
lw t5, -20(t0) # t5 <-- _gp
sub t4, t5 # compute offset
add t4, t4, gp # t4 now holds relocated _G_O_T_
addi t4, t4, 8 # skipping first two entries
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
li t2, 2
1:
lw t1, 0(t4)
beqz t1, 2f
MIPS: Coding style cleanups on common assembly files Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-06 15:18:13 +00:00
add t1, s1
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
sw t1, 0(t4)
2:
addi t2, 1
blt t2, t3, 1b
MIPS: Coding style cleanups on common assembly files Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-06 15:18:13 +00:00
addi t4, 4
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
MIPS: Coding style cleanups on common assembly files Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-06 15:18:13 +00:00
/* Clear BSS */
lw t1, -12(t0) # t1 <-- uboot_end_data
lw t2, -8(t0) # t2 <-- uboot_end
add t1, s1 # adjust pointers
MIPS: Flush data cache upon relocation This patch now adds a flush to the data cache upon relocation. The current implementation is missing this. Only a comment states that it should be done. So let's really do it now. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2008-11-18 15:36:12 +00:00
add t2, s1
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
sub t1, 4
[MIPS] MIPS 4K core: Coding style cleanups No logical changes. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2007-10-27 06:27:06 +00:00
1:
addi t1, 4
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
bltl t1, t2, 1b
MIPS: Coding style cleanups on common assembly files Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-06 15:18:13 +00:00
sw zero, 0(t1)
* Code cleanup: - remove trailing white space, trailing empty lines, C++ comments, etc. - split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c) * Patches by Kenneth Johansson, 25 Jun 2003: - major rework of command structure (work done mostly by Michal Cendrowski and Joakim Kristiansen)
2003-06-27 21:31:46 +00:00
MIPS: Coding style cleanups on common assembly files Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-06 15:18:13 +00:00
move a0, s0 # a0 <-- gd
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
la t9, board_init_r
Use jr as register jump instruction Current assembler codes are inconsistent in the way of register jump instruction usage; some use jr, some use j. Of course GNU as allows both usages, but as can be expected from `Jump Register' the mnemonic `jr' is more intuitive than `j'. For example, Linux doesn't have `j <reg>' usage at all. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2008-04-17 14:35:13 +00:00
jr t9
MIPS: Coding style cleanups on common assembly files Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-06 15:18:13 +00:00
move a1, s2
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
.end relocate_code
MIPS: Coding style cleanups on common assembly files Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-06 15:18:13 +00:00
/* Exception handlers */
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
romReserved:
[MIPS] MIPS 4K core: Coding style cleanups No logical changes. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2007-10-27 06:27:06 +00:00
b romReserved
MIPS: start{, 64}.S: fill branch delay slots with NOP instructions The romReserved and romExcHandle handlers are accessed by a branch instruction however the delay slots of those instructions are not filled. Because the start.S uses the 'noreorder' directive, the assembler will not fill the delay slots either, and leads to the following assembly code: 0000056c <romReserved>: 56c: 1000ffff b 56c <romReserved> 00000570 <romExcHandle>: 570: 1000ffff b 570 <romExcHandle> In the resulting code, the second branch instruction is placed into the delay slot of the first branch instruction, which is not allowed on the MIPS architecture. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-16 03:05:01 +00:00
nop
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
romExcHandle:
[MIPS] MIPS 4K core: Coding style cleanups No logical changes. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2007-10-27 06:27:06 +00:00
b romExcHandle
MIPS: start{, 64}.S: fill branch delay slots with NOP instructions The romReserved and romExcHandle handlers are accessed by a branch instruction however the delay slots of those instructions are not filled. Because the start.S uses the 'noreorder' directive, the assembler will not fill the delay slots either, and leads to the following assembly code: 0000056c <romReserved>: 56c: 1000ffff b 56c <romReserved> 00000570 <romExcHandle>: 570: 1000ffff b 570 <romExcHandle> In the resulting code, the second branch instruction is placed into the delay slot of the first branch instruction, which is not allowed on the MIPS architecture. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-01-16 03:05:01 +00:00
nop
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