2008-12-14 08:47:13 +00:00
|
|
|
/*
|
|
|
|
* armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
|
|
|
|
*
|
|
|
|
* Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
|
|
|
|
*
|
|
|
|
* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
|
|
|
|
* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
|
2009-05-13 08:54:10 +00:00
|
|
|
* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
|
2008-12-14 08:47:13 +00:00
|
|
|
* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
|
|
|
|
* Copyright (c) 2003 Kshitij <kshitij@ti.com>
|
|
|
|
* Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
|
|
|
|
*
|
2013-07-08 07:37:19 +00:00
|
|
|
* SPDX-License-Identifier: GPL-2.0+
|
2008-12-14 08:47:13 +00:00
|
|
|
*/
|
|
|
|
|
2010-10-26 12:34:52 +00:00
|
|
|
#include <asm-offsets.h>
|
2008-12-14 08:47:13 +00:00
|
|
|
#include <config.h>
|
|
|
|
#include <version.h>
|
2011-11-21 23:34:00 +00:00
|
|
|
#include <asm/system.h>
|
2012-03-08 07:20:18 +00:00
|
|
|
#include <linux/linkage.h>
|
2008-12-14 08:47:13 +00:00
|
|
|
|
|
|
|
.globl _start
|
|
|
|
_start: b reset
|
|
|
|
ldr pc, _undefined_instruction
|
|
|
|
ldr pc, _software_interrupt
|
|
|
|
ldr pc, _prefetch_abort
|
|
|
|
ldr pc, _data_abort
|
|
|
|
ldr pc, _not_used
|
|
|
|
ldr pc, _irq
|
|
|
|
ldr pc, _fiq
|
2011-07-21 13:10:18 +00:00
|
|
|
#ifdef CONFIG_SPL_BUILD
|
|
|
|
_undefined_instruction: .word _undefined_instruction
|
|
|
|
_software_interrupt: .word _software_interrupt
|
|
|
|
_prefetch_abort: .word _prefetch_abort
|
|
|
|
_data_abort: .word _data_abort
|
|
|
|
_not_used: .word _not_used
|
|
|
|
_irq: .word _irq
|
|
|
|
_fiq: .word _fiq
|
|
|
|
_pad: .word 0x12345678 /* now 16*4=64 */
|
|
|
|
#else
|
2008-12-14 08:47:13 +00:00
|
|
|
_undefined_instruction: .word undefined_instruction
|
|
|
|
_software_interrupt: .word software_interrupt
|
|
|
|
_prefetch_abort: .word prefetch_abort
|
|
|
|
_data_abort: .word data_abort
|
|
|
|
_not_used: .word not_used
|
|
|
|
_irq: .word irq
|
|
|
|
_fiq: .word fiq
|
|
|
|
_pad: .word 0x12345678 /* now 16*4=64 */
|
2011-07-21 13:10:18 +00:00
|
|
|
#endif /* CONFIG_SPL_BUILD */
|
|
|
|
|
2008-12-14 08:47:13 +00:00
|
|
|
.global _end_vect
|
|
|
|
_end_vect:
|
|
|
|
|
|
|
|
.balignl 16,0xdeadbeef
|
|
|
|
/*************************************************************************
|
|
|
|
*
|
|
|
|
* Startup Code (reset vector)
|
|
|
|
*
|
|
|
|
* do important init only if we don't start from memory!
|
|
|
|
* setup Memory and board specific bits prior to relocation.
|
|
|
|
* relocate armboot to ram
|
|
|
|
* setup stack
|
|
|
|
*
|
|
|
|
*************************************************************************/
|
|
|
|
|
2010-09-17 11:10:41 +00:00
|
|
|
.globl _TEXT_BASE
|
2008-12-14 08:47:13 +00:00
|
|
|
_TEXT_BASE:
|
2013-04-11 09:35:42 +00:00
|
|
|
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
|
|
|
|
.word CONFIG_SPL_TEXT_BASE
|
|
|
|
#else
|
2010-10-07 19:51:12 +00:00
|
|
|
.word CONFIG_SYS_TEXT_BASE
|
2013-04-11 09:35:42 +00:00
|
|
|
#endif
|
2008-12-14 08:47:13 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* These are defined in the board-specific linker script.
|
|
|
|
*/
|
2010-10-11 12:08:15 +00:00
|
|
|
.globl _bss_start_ofs
|
|
|
|
_bss_start_ofs:
|
|
|
|
.word __bss_start - _start
|
2008-12-14 08:47:13 +00:00
|
|
|
|
2010-10-11 12:08:15 +00:00
|
|
|
.globl _bss_end_ofs
|
|
|
|
_bss_end_ofs:
|
2013-03-14 06:54:53 +00:00
|
|
|
.word __bss_end - _start
|
2008-12-14 08:47:13 +00:00
|
|
|
|
2011-03-01 23:02:04 +00:00
|
|
|
.globl _end_ofs
|
|
|
|
_end_ofs:
|
|
|
|
.word _end - _start
|
|
|
|
|
2008-12-14 08:47:13 +00:00
|
|
|
#ifdef CONFIG_USE_IRQ
|
|
|
|
/* IRQ stack memory (calculated at run-time) */
|
|
|
|
.globl IRQ_STACK_START
|
|
|
|
IRQ_STACK_START:
|
|
|
|
.word 0x0badc0de
|
|
|
|
|
|
|
|
/* IRQ stack memory (calculated at run-time) */
|
|
|
|
.globl FIQ_STACK_START
|
|
|
|
FIQ_STACK_START:
|
|
|
|
.word 0x0badc0de
|
|
|
|
#endif
|
|
|
|
|
2010-09-17 11:10:41 +00:00
|
|
|
/* IRQ stack memory (calculated at run-time) + 8 bytes */
|
|
|
|
.globl IRQ_STACK_START_IN
|
|
|
|
IRQ_STACK_START_IN:
|
|
|
|
.word 0x0badc0de
|
|
|
|
|
|
|
|
/*
|
|
|
|
* the actual reset code
|
|
|
|
*/
|
|
|
|
|
|
|
|
reset:
|
2011-07-21 13:10:27 +00:00
|
|
|
bl save_boot_params
|
2010-09-17 11:10:41 +00:00
|
|
|
/*
|
2013-04-02 05:43:36 +00:00
|
|
|
* disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
|
|
|
|
* except if in HYP mode already
|
2010-09-17 11:10:41 +00:00
|
|
|
*/
|
|
|
|
mrs r0, cpsr
|
2013-04-02 05:43:36 +00:00
|
|
|
and r1, r0, #0x1f @ mask mode bits
|
|
|
|
teq r1, #0x1a @ test for HYP mode
|
|
|
|
bicne r0, r0, #0x1f @ clear all mode bits
|
|
|
|
orrne r0, r0, #0x13 @ set SVC mode
|
|
|
|
orr r0, r0, #0xc0 @ disable FIQ and IRQ
|
2010-09-17 11:10:41 +00:00
|
|
|
msr cpsr,r0
|
|
|
|
|
2011-11-21 23:34:00 +00:00
|
|
|
/*
|
|
|
|
* Setup vector:
|
|
|
|
* (OMAP4 spl TEXT_BASE is not 32 byte aligned.
|
|
|
|
* Continue to use ROM code vector only in OMAP4 spl)
|
|
|
|
*/
|
|
|
|
#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
|
|
|
|
/* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */
|
|
|
|
mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTRL Register
|
|
|
|
bic r0, #CR_V @ V = 0
|
|
|
|
mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTRL Register
|
|
|
|
|
|
|
|
/* Set vector address in CP15 VBAR register */
|
|
|
|
ldr r0, =_start
|
|
|
|
mcr p15, 0, r0, c12, c0, 0 @Set VBAR
|
|
|
|
#endif
|
|
|
|
|
2010-09-17 11:10:41 +00:00
|
|
|
/* the mask ROM code should have PLL and others stable */
|
|
|
|
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
2011-11-05 03:56:51 +00:00
|
|
|
bl cpu_init_cp15
|
2010-09-17 11:10:41 +00:00
|
|
|
bl cpu_init_crit
|
|
|
|
#endif
|
|
|
|
|
2013-01-08 10:18:02 +00:00
|
|
|
bl _main
|
2010-09-17 11:10:41 +00:00
|
|
|
|
|
|
|
/*------------------------------------------------------------------------------*/
|
|
|
|
|
2013-01-08 10:18:02 +00:00
|
|
|
ENTRY(c_runtime_cpu_setup)
|
2011-06-16 23:30:49 +00:00
|
|
|
/*
|
|
|
|
* If I-cache is enabled invalidate it
|
|
|
|
*/
|
|
|
|
#ifndef CONFIG_SYS_ICACHE_OFF
|
|
|
|
mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
|
|
|
|
mcr p15, 0, r0, c7, c10, 4 @ DSB
|
|
|
|
mcr p15, 0, r0, c7, c5, 4 @ ISB
|
|
|
|
#endif
|
2012-06-25 02:40:57 +00:00
|
|
|
/*
|
|
|
|
* Move vector table
|
|
|
|
*/
|
|
|
|
/* Set vector address in CP15 VBAR register */
|
|
|
|
ldr r0, =_start
|
|
|
|
mcr p15, 0, r0, c12, c0, 0 @Set VBAR
|
|
|
|
|
2013-01-08 10:18:02 +00:00
|
|
|
bx lr
|
|
|
|
|
|
|
|
ENDPROC(c_runtime_cpu_setup)
|
2010-10-11 12:08:15 +00:00
|
|
|
|
2012-07-06 21:14:20 +00:00
|
|
|
/*************************************************************************
|
|
|
|
*
|
|
|
|
* void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
|
|
|
|
* __attribute__((weak));
|
|
|
|
*
|
|
|
|
* Stack pointer is not yet initialized at this moment
|
|
|
|
* Don't save anything to stack even if compiled with -O0
|
|
|
|
*
|
|
|
|
*************************************************************************/
|
|
|
|
ENTRY(save_boot_params)
|
|
|
|
bx lr @ back to my caller
|
|
|
|
ENDPROC(save_boot_params)
|
|
|
|
.weak save_boot_params
|
|
|
|
|
2008-12-14 08:47:13 +00:00
|
|
|
/*************************************************************************
|
|
|
|
*
|
2011-11-05 03:56:51 +00:00
|
|
|
* cpu_init_cp15
|
2008-12-14 08:47:13 +00:00
|
|
|
*
|
2011-11-05 03:56:51 +00:00
|
|
|
* Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
|
|
|
|
* CONFIG_SYS_ICACHE_OFF is defined.
|
2008-12-14 08:47:13 +00:00
|
|
|
*
|
|
|
|
*************************************************************************/
|
2012-03-08 07:20:18 +00:00
|
|
|
ENTRY(cpu_init_cp15)
|
2008-12-14 08:47:13 +00:00
|
|
|
/*
|
|
|
|
* Invalidate L1 I/D
|
|
|
|
*/
|
|
|
|
mov r0, #0 @ set up for MCR
|
|
|
|
mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
|
|
|
|
mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
|
2011-06-16 23:30:49 +00:00
|
|
|
mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
|
|
|
|
mcr p15, 0, r0, c7, c10, 4 @ DSB
|
|
|
|
mcr p15, 0, r0, c7, c5, 4 @ ISB
|
2008-12-14 08:47:13 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* disable MMU stuff and caches
|
|
|
|
*/
|
|
|
|
mrc p15, 0, r0, c1, c0, 0
|
|
|
|
bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
|
|
|
|
bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
|
|
|
|
orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
|
2011-06-16 23:30:49 +00:00
|
|
|
orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
|
|
|
|
#ifdef CONFIG_SYS_ICACHE_OFF
|
|
|
|
bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
|
|
|
|
#else
|
|
|
|
orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
|
|
|
|
#endif
|
2008-12-14 08:47:13 +00:00
|
|
|
mcr p15, 0, r0, c1, c0, 0
|
2013-02-26 12:28:27 +00:00
|
|
|
|
2013-03-04 13:29:40 +00:00
|
|
|
#ifdef CONFIG_ARM_ERRATA_716044
|
|
|
|
mrc p15, 0, r0, c1, c0, 0 @ read system control register
|
|
|
|
orr r0, r0, #1 << 11 @ set bit #11
|
|
|
|
mcr p15, 0, r0, c1, c0, 0 @ write system control register
|
|
|
|
#endif
|
|
|
|
|
2013-02-26 12:28:27 +00:00
|
|
|
#ifdef CONFIG_ARM_ERRATA_742230
|
|
|
|
mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
|
|
|
|
orr r0, r0, #1 << 4 @ set bit #4
|
|
|
|
mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef CONFIG_ARM_ERRATA_743622
|
|
|
|
mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
|
|
|
|
orr r0, r0, #1 << 6 @ set bit #6
|
|
|
|
mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef CONFIG_ARM_ERRATA_751472
|
|
|
|
mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
|
|
|
|
orr r0, r0, #1 << 11 @ set bit #11
|
|
|
|
mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
|
|
|
|
#endif
|
|
|
|
|
2011-11-05 03:56:51 +00:00
|
|
|
mov pc, lr @ back to my caller
|
2012-03-08 07:20:18 +00:00
|
|
|
ENDPROC(cpu_init_cp15)
|
2008-12-14 08:47:13 +00:00
|
|
|
|
2011-11-05 03:56:51 +00:00
|
|
|
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
|
|
|
/*************************************************************************
|
|
|
|
*
|
|
|
|
* CPU_init_critical registers
|
|
|
|
*
|
|
|
|
* setup important registers
|
|
|
|
* setup memory timing
|
|
|
|
*
|
|
|
|
*************************************************************************/
|
2012-03-08 07:20:18 +00:00
|
|
|
ENTRY(cpu_init_crit)
|
2008-12-14 08:47:13 +00:00
|
|
|
/*
|
|
|
|
* Jump to board specific initialization...
|
|
|
|
* The Mask ROM will have already initialized
|
|
|
|
* basic memory. Go here to bump up clock rate and handle
|
|
|
|
* wake up conditions.
|
|
|
|
*/
|
2012-08-10 12:05:16 +00:00
|
|
|
b lowlevel_init @ go setup pll,mux,memory
|
2012-03-08 07:20:18 +00:00
|
|
|
ENDPROC(cpu_init_crit)
|
2011-06-28 05:39:38 +00:00
|
|
|
#endif
|
2011-07-21 13:10:18 +00:00
|
|
|
|
|
|
|
#ifndef CONFIG_SPL_BUILD
|
2008-12-14 08:47:13 +00:00
|
|
|
/*
|
|
|
|
*************************************************************************
|
|
|
|
*
|
|
|
|
* Interrupt handling
|
|
|
|
*
|
|
|
|
*************************************************************************
|
|
|
|
*/
|
|
|
|
@
|
|
|
|
@ IRQ stack frame.
|
|
|
|
@
|
|
|
|
#define S_FRAME_SIZE 72
|
|
|
|
|
|
|
|
#define S_OLD_R0 68
|
|
|
|
#define S_PSR 64
|
|
|
|
#define S_PC 60
|
|
|
|
#define S_LR 56
|
|
|
|
#define S_SP 52
|
|
|
|
|
|
|
|
#define S_IP 48
|
|
|
|
#define S_FP 44
|
|
|
|
#define S_R10 40
|
|
|
|
#define S_R9 36
|
|
|
|
#define S_R8 32
|
|
|
|
#define S_R7 28
|
|
|
|
#define S_R6 24
|
|
|
|
#define S_R5 20
|
|
|
|
#define S_R4 16
|
|
|
|
#define S_R3 12
|
|
|
|
#define S_R2 8
|
|
|
|
#define S_R1 4
|
|
|
|
#define S_R0 0
|
|
|
|
|
|
|
|
#define MODE_SVC 0x13
|
|
|
|
#define I_BIT 0x80
|
|
|
|
|
|
|
|
/*
|
|
|
|
* use bad_save_user_regs for abort/prefetch/undef/swi ...
|
|
|
|
* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
|
|
|
|
*/
|
|
|
|
|
|
|
|
.macro bad_save_user_regs
|
|
|
|
sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current
|
|
|
|
@ user stack
|
|
|
|
stmia sp, {r0 - r12} @ Save user registers (now in
|
|
|
|
@ svc mode) r0-r12
|
2010-09-17 11:10:41 +00:00
|
|
|
ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort
|
2008-12-14 08:47:13 +00:00
|
|
|
@ stack
|
|
|
|
ldmia r2, {r2 - r3} @ get values for "aborted" pc
|
|
|
|
@ and cpsr (into parm regs)
|
|
|
|
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
|
|
|
|
|
|
|
|
add r5, sp, #S_SP
|
|
|
|
mov r1, lr
|
|
|
|
stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
|
|
|
|
mov r0, sp @ save current stack into r0
|
|
|
|
@ (param register)
|
|
|
|
.endm
|
|
|
|
|
|
|
|
.macro irq_save_user_regs
|
|
|
|
sub sp, sp, #S_FRAME_SIZE
|
|
|
|
stmia sp, {r0 - r12} @ Calling r0-r12
|
|
|
|
add r8, sp, #S_PC @ !! R8 NEEDS to be saved !!
|
|
|
|
@ a reserved stack spot would
|
|
|
|
@ be good.
|
|
|
|
stmdb r8, {sp, lr}^ @ Calling SP, LR
|
|
|
|
str lr, [r8, #0] @ Save calling PC
|
|
|
|
mrs r6, spsr
|
|
|
|
str r6, [r8, #4] @ Save CPSR
|
|
|
|
str r0, [r8, #8] @ Save OLD_R0
|
|
|
|
mov r0, sp
|
|
|
|
.endm
|
|
|
|
|
|
|
|
.macro irq_restore_user_regs
|
|
|
|
ldmia sp, {r0 - lr}^ @ Calling r0 - lr
|
|
|
|
mov r0, r0
|
|
|
|
ldr lr, [sp, #S_PC] @ Get PC
|
|
|
|
add sp, sp, #S_FRAME_SIZE
|
|
|
|
subs pc, lr, #4 @ return & move spsr_svc into
|
|
|
|
@ cpsr
|
|
|
|
.endm
|
|
|
|
|
|
|
|
.macro get_bad_stack
|
2010-09-17 11:10:41 +00:00
|
|
|
ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter
|
|
|
|
@ in banked mode)
|
2008-12-14 08:47:13 +00:00
|
|
|
|
|
|
|
str lr, [r13] @ save caller lr in position 0
|
|
|
|
@ of saved stack
|
|
|
|
mrs lr, spsr @ get the spsr
|
|
|
|
str lr, [r13, #4] @ save spsr in position 1 of
|
|
|
|
@ saved stack
|
|
|
|
|
|
|
|
mov r13, #MODE_SVC @ prepare SVC-Mode
|
|
|
|
@ msr spsr_c, r13
|
|
|
|
msr spsr, r13 @ switch modes, make sure
|
|
|
|
@ moves will execute
|
|
|
|
mov lr, pc @ capture return pc
|
|
|
|
movs pc, lr @ jump to next instruction &
|
|
|
|
@ switch modes.
|
|
|
|
.endm
|
|
|
|
|
|
|
|
.macro get_bad_stack_swi
|
|
|
|
sub r13, r13, #4 @ space on current stack for
|
|
|
|
@ scratch reg.
|
|
|
|
str r0, [r13] @ save R0's value.
|
2010-09-17 11:10:41 +00:00
|
|
|
ldr r0, IRQ_STACK_START_IN @ get data regions start
|
2008-12-14 08:47:13 +00:00
|
|
|
@ spots for abort stack
|
|
|
|
str lr, [r0] @ save caller lr in position 0
|
|
|
|
@ of saved stack
|
2013-04-05 00:12:51 +00:00
|
|
|
mrs lr, spsr @ get the spsr
|
2008-12-14 08:47:13 +00:00
|
|
|
str lr, [r0, #4] @ save spsr in position 1 of
|
|
|
|
@ saved stack
|
2013-04-05 00:12:51 +00:00
|
|
|
ldr lr, [r0] @ restore lr
|
2008-12-14 08:47:13 +00:00
|
|
|
ldr r0, [r13] @ restore r0
|
|
|
|
add r13, r13, #4 @ pop stack entry
|
|
|
|
.endm
|
|
|
|
|
|
|
|
.macro get_irq_stack @ setup IRQ stack
|
|
|
|
ldr sp, IRQ_STACK_START
|
|
|
|
.endm
|
|
|
|
|
|
|
|
.macro get_fiq_stack @ setup FIQ stack
|
|
|
|
ldr sp, FIQ_STACK_START
|
|
|
|
.endm
|
|
|
|
|
|
|
|
/*
|
|
|
|
* exception handlers
|
|
|
|
*/
|
|
|
|
.align 5
|
|
|
|
undefined_instruction:
|
|
|
|
get_bad_stack
|
|
|
|
bad_save_user_regs
|
|
|
|
bl do_undefined_instruction
|
|
|
|
|
|
|
|
.align 5
|
|
|
|
software_interrupt:
|
|
|
|
get_bad_stack_swi
|
|
|
|
bad_save_user_regs
|
|
|
|
bl do_software_interrupt
|
|
|
|
|
|
|
|
.align 5
|
|
|
|
prefetch_abort:
|
|
|
|
get_bad_stack
|
|
|
|
bad_save_user_regs
|
|
|
|
bl do_prefetch_abort
|
|
|
|
|
|
|
|
.align 5
|
|
|
|
data_abort:
|
|
|
|
get_bad_stack
|
|
|
|
bad_save_user_regs
|
|
|
|
bl do_data_abort
|
|
|
|
|
|
|
|
.align 5
|
|
|
|
not_used:
|
|
|
|
get_bad_stack
|
|
|
|
bad_save_user_regs
|
|
|
|
bl do_not_used
|
|
|
|
|
|
|
|
#ifdef CONFIG_USE_IRQ
|
|
|
|
|
|
|
|
.align 5
|
|
|
|
irq:
|
|
|
|
get_irq_stack
|
|
|
|
irq_save_user_regs
|
|
|
|
bl do_irq
|
|
|
|
irq_restore_user_regs
|
|
|
|
|
|
|
|
.align 5
|
|
|
|
fiq:
|
|
|
|
get_fiq_stack
|
|
|
|
/* someone ought to write a more effective fiq_save_user_regs */
|
|
|
|
irq_save_user_regs
|
|
|
|
bl do_fiq
|
|
|
|
irq_restore_user_regs
|
|
|
|
|
|
|
|
#else
|
|
|
|
|
|
|
|
.align 5
|
|
|
|
irq:
|
|
|
|
get_bad_stack
|
|
|
|
bad_save_user_regs
|
|
|
|
bl do_irq
|
|
|
|
|
|
|
|
.align 5
|
|
|
|
fiq:
|
|
|
|
get_bad_stack
|
|
|
|
bad_save_user_regs
|
|
|
|
bl do_fiq
|
|
|
|
|
2011-07-21 13:10:18 +00:00
|
|
|
#endif /* CONFIG_USE_IRQ */
|
|
|
|
#endif /* CONFIG_SPL_BUILD */
|