2018-03-27 13:43:05 +02:00
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// SPDX-License-Identifier: GPL-2.0+
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2014-01-09 01:48:29 +05:30
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/*
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* Xilinx ZC770 XM012 board DTS
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*
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2018-03-27 13:43:05 +02:00
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* Copyright (C) 2013-2018 Xilinx, Inc.
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2014-01-09 01:48:29 +05:30
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*/
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/dts-v1/;
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#include "zynq-7000.dtsi"
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/ {
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2018-07-12 00:10:20 -04:00
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model = "Xilinx ZC770 XM012 board";
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2014-01-09 01:48:29 +05:30
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compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000";
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2014-05-15 20:37:54 +09:00
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2014-05-15 20:37:55 +09:00
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aliases {
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2015-07-22 11:36:32 +02:00
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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2014-05-15 20:37:55 +09:00
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serial0 = &uart1;
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2015-07-22 11:36:32 +02:00
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spi0 = &spi1;
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2014-05-15 20:37:55 +09:00
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};
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2015-07-22 11:36:32 +02:00
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chosen {
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2016-04-07 11:15:00 +02:00
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bootargs = "";
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2016-01-12 13:56:44 +01:00
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stdout-path = "serial0:115200n8";
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2015-07-22 11:36:32 +02:00
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};
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2016-11-11 13:11:37 +01:00
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memory@0 {
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2014-05-15 20:37:54 +09:00
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device_type = "memory";
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2015-07-22 11:36:32 +02:00
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reg = <0x0 0x40000000>;
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};
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};
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&can1 {
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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clock-frequency = <400000>;
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2018-03-27 13:48:51 +02:00
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eeprom0: eeprom@52 {
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compatible = "atmel,24c02";
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2015-07-22 11:36:32 +02:00
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reg = <0x52>;
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};
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};
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&i2c1 {
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status = "okay";
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clock-frequency = <400000>;
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2018-03-27 13:48:51 +02:00
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eeprom1: eeprom@52 {
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compatible = "atmel,24c02";
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2015-07-22 11:36:32 +02:00
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reg = <0x52>;
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2014-05-15 20:37:54 +09:00
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};
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2014-01-09 01:48:29 +05:30
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};
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2015-07-22 11:36:32 +02:00
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2016-01-14 13:09:16 +01:00
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&spi1 {
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status = "okay";
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num-cs = <4>;
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is-decoded-cs = <0>;
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};
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2015-07-22 11:36:32 +02:00
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&uart1 {
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2015-10-17 19:41:24 -06:00
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u-boot,dm-pre-reloc;
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2015-07-22 11:36:32 +02:00
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status = "okay";
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};
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