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34 lines
1.2 KiB
C
34 lines
1.2 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* R-Car Gen3 Clock Pulse Generator Library
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*
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* Copyright (C) 2015-2018 Glider bvba
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* Copyright (C) 2019 Renesas Electronics Corp.
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*
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* Based on clk-rcar-gen3.c
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*
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* Copyright (C) 2015 Renesas Electronics Corp.
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*/
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#ifndef __CLK_RENESAS_RCAR_CPG_LIB_H__
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#define __CLK_RENESAS_RCAR_CPG_LIB_H__
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s64 rcar_clk_get_rate64_div_table(unsigned int parent, u64 parent_rate,
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void __iomem *reg, const u32 mask,
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const struct clk_div_table *table, char *name);
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int rcar_clk_set_rate64_div_table(unsigned int parent, u64 parent_rate, ulong rate,
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void __iomem *reg, const u32 mask,
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const struct clk_div_table *table, char *name);
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s64 rcar_clk_get_rate64_sdh(unsigned int parent, u64 parent_rate, void __iomem *reg);
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s64 rcar_clk_get_rate64_sd(unsigned int parent, u64 parent_rate, void __iomem *reg);
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s64 rcar_clk_get_rate64_rpc(unsigned int parent, u64 parent_rate, void __iomem *reg);
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u64 rcar_clk_get_rate64_rpcd2(unsigned int parent, u64 parent_rate);
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int rcar_clk_set_rate64_sdh(unsigned int parent, u64 parent_rate, ulong rate,
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void __iomem *reg);
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int rcar_clk_set_rate64_sd(unsigned int parent, u64 parent_rate, ulong rate,
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void __iomem *reg);
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#endif
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