2018-11-20 10:20:00 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2018 NXP
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*/
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#ifndef __IMX8M_EVK_H
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#define __IMX8M_EVK_H
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#include <linux/sizes.h>
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2020-05-10 17:40:09 +00:00
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#include <linux/stringify.h>
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2018-11-20 10:20:00 +00:00
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#include <asm/arch/imx-regs.h>
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2021-08-29 19:39:12 +00:00
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#define CONFIG_SYS_BOOTM_LEN (64 * SZ_1M)
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2020-07-28 09:28:57 +00:00
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2018-11-20 10:20:00 +00:00
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#define CONFIG_SPL_MAX_SIZE (124 * 1024)
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#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
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#ifdef CONFIG_SPL_BUILD
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/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
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#define CONFIG_SPL_STACK 0x187FF0
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#define CONFIG_SPL_BSS_START_ADDR 0x00180000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
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#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */
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#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000
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/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
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#define CONFIG_MALLOC_F_ADDR 0x182000
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/* For RAW image gives a error info not panic */
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#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
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#undef CONFIG_DM_MMC
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#define CONFIG_POWER_PFUZE100
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#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
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#endif
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/* ENET Config */
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/* ENET1 */
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#if defined(CONFIG_CMD_NET)
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#define CONFIG_ETHPRIME "FEC"
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#define CONFIG_FEC_XCV_TYPE RGMII
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#define CONFIG_FEC_MXC_PHYADDR 0
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#define FEC_QUIRK_ENET_MAC
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#define IMX_FEC_BASE 0x30BE0000
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#endif
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2021-01-14 08:23:23 +00:00
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#ifndef CONFIG_SPL_BUILD
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#define BOOT_TARGET_DEVICES(func) \
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func(MMC, mmc, 0) \
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func(MMC, mmc, 1) \
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func(DHCP, dhcp, na)
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#include <config_distro_bootcmd.h>
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#endif
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2018-11-20 10:20:00 +00:00
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/* Initial environment variables */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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2021-01-14 08:23:23 +00:00
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BOOTENV \
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2022-01-16 21:38:31 +00:00
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"scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
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"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
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2018-11-20 10:20:00 +00:00
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"image=Image\0" \
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2019-12-11 17:31:03 +00:00
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"console=ttymxc0,115200\0" \
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2022-01-16 21:38:31 +00:00
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"fdt_addr_r=0x43000000\0" \
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2018-11-20 10:20:00 +00:00
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"boot_fdt=try\0" \
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2022-01-16 21:38:31 +00:00
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"fdtfile=imx8mq-evk.dtb\0" \
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2018-11-20 10:20:00 +00:00
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"initrd_addr=0x43800000\0" \
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2020-08-21 13:39:43 +00:00
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"bootm_size=0x10000000\0" \
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2021-12-11 19:55:52 +00:00
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"mmcpart=1\0" \
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2018-11-20 10:20:00 +00:00
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"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
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/* Link Definitions */
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#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
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#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
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#define CONFIG_SYS_SDRAM_BASE 0x40000000
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#define PHYS_SDRAM 0x40000000
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#define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */
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#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
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/* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 1024
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#define CONFIG_SYS_MAXARGS 64
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_FSL_USDHC_NUM 2
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#define CONFIG_SYS_FSL_ESDHC_ADDR 0
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#endif
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