2018-05-06 21:58:06 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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2015-10-28 10:46:32 +00:00
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/*
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* (C) Copyright 2014
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2018-03-06 07:04:58 +00:00
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* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
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2015-10-28 10:46:32 +00:00
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*/
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#include <common.h>
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#include <gdsys_fpga.h>
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enum {
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UNITTYPE_MAIN_SERVER = 0,
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UNITTYPE_MAIN_USER = 1,
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UNITTYPE_VIDEO_SERVER = 2,
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UNITTYPE_VIDEO_USER = 3,
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};
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enum {
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UNITTYPEPCB_DVI = 0,
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UNITTYPEPCB_DP_165 = 1,
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UNITTYPEPCB_DP_300 = 2,
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UNITTYPEPCB_HDMI = 3,
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};
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enum {
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COMPRESSION_NONE = 0,
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2016-06-02 07:05:39 +00:00
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COMPRESSION_TYPE_1 = 1,
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COMPRESSION_TYPE_1_2 = 3,
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COMPRESSION_TYPE_1_2_3 = 7,
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2015-10-28 10:46:32 +00:00
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};
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enum {
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AUDIO_NONE = 0,
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AUDIO_TX = 1,
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AUDIO_RX = 2,
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AUDIO_RXTX = 3,
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};
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enum {
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SYSCLK_147456 = 0,
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};
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enum {
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RAM_DDR2_32 = 0,
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RAM_DDR3_32 = 1,
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2015-10-28 10:46:33 +00:00
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RAM_DDR3_48 = 2,
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2015-10-28 10:46:32 +00:00
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};
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enum {
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CARRIER_SPEED_1G = 0,
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CARRIER_SPEED_2_5G = 1,
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};
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bool ioep_fpga_has_osd(unsigned int fpga)
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{
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u16 fpga_features;
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unsigned feature_osd;
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FPGA_GET_REG(0, fpga_features, &fpga_features);
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feature_osd = fpga_features & (1<<11);
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return feature_osd;
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}
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void ioep_fpga_print_info(unsigned int fpga)
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{
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u16 versions;
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u16 fpga_version;
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u16 fpga_features;
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unsigned unit_type;
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unsigned unit_type_pcb_video;
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unsigned feature_compression;
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unsigned feature_osd;
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unsigned feature_audio;
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unsigned feature_sysclock;
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unsigned feature_ramconfig;
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unsigned feature_carrier_speed;
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unsigned feature_carriers;
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unsigned feature_video_channels;
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FPGA_GET_REG(fpga, versions, &versions);
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FPGA_GET_REG(fpga, fpga_version, &fpga_version);
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FPGA_GET_REG(fpga, fpga_features, &fpga_features);
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unit_type = (versions & 0xf000) >> 12;
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unit_type_pcb_video = (versions & 0x01c0) >> 6;
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feature_compression = (fpga_features & 0xe000) >> 13;
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feature_osd = fpga_features & (1<<11);
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feature_audio = (fpga_features & 0x0600) >> 9;
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feature_sysclock = (fpga_features & 0x0180) >> 7;
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feature_ramconfig = (fpga_features & 0x0060) >> 5;
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feature_carrier_speed = fpga_features & (1<<4);
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feature_carriers = (fpga_features & 0x000c) >> 2;
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feature_video_channels = fpga_features & 0x0003;
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switch (unit_type) {
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case UNITTYPE_MAIN_SERVER:
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case UNITTYPE_MAIN_USER:
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printf("Mainchannel");
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break;
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case UNITTYPE_VIDEO_SERVER:
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case UNITTYPE_VIDEO_USER:
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printf("Videochannel");
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break;
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default:
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printf("UnitType %d(not supported)", unit_type);
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break;
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}
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switch (unit_type) {
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case UNITTYPE_MAIN_SERVER:
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case UNITTYPE_VIDEO_SERVER:
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printf(" Server");
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if (versions & (1<<4))
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printf(" UC");
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break;
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case UNITTYPE_MAIN_USER:
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case UNITTYPE_VIDEO_USER:
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printf(" User");
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break;
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default:
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break;
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}
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if (versions & (1<<5))
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printf(" Fiber");
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else
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printf(" CAT");
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switch (unit_type_pcb_video) {
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case UNITTYPEPCB_DVI:
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printf(" DVI,");
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break;
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case UNITTYPEPCB_DP_165:
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printf(" DP 165MPix/s,");
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break;
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case UNITTYPEPCB_DP_300:
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printf(" DP 300MPix/s,");
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break;
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case UNITTYPEPCB_HDMI:
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printf(" HDMI,");
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break;
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}
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printf(" FPGA V %d.%02d\n features:",
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fpga_version / 100, fpga_version % 100);
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switch (feature_compression) {
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case COMPRESSION_NONE:
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printf(" no compression");
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break;
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2016-06-02 07:05:39 +00:00
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case COMPRESSION_TYPE_1:
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printf(" compression type1(delta)");
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2015-10-28 10:46:32 +00:00
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break;
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2016-06-02 07:05:39 +00:00
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case COMPRESSION_TYPE_1_2:
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printf(" compression type1(delta), type2(inline)");
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break;
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case COMPRESSION_TYPE_1_2_3:
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printf(" compression type1(delta), type2(inline), type3(intempo)");
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2015-10-28 10:46:32 +00:00
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break;
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default:
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printf(" compression %d(not supported)", feature_compression);
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break;
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}
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printf(", %sosd", feature_osd ? "" : "no ");
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switch (feature_audio) {
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case AUDIO_NONE:
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printf(", no audio");
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break;
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case AUDIO_TX:
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printf(", audio tx");
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break;
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case AUDIO_RX:
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printf(", audio rx");
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break;
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case AUDIO_RXTX:
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printf(", audio rx+tx");
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break;
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default:
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printf(", audio %d(not supported)", feature_audio);
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break;
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}
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puts(",\n ");
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switch (feature_sysclock) {
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case SYSCLK_147456:
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printf("clock 147.456 MHz");
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break;
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default:
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printf("clock %d(not supported)", feature_sysclock);
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break;
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}
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switch (feature_ramconfig) {
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case RAM_DDR2_32:
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printf(", RAM 32 bit DDR2");
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break;
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case RAM_DDR3_32:
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printf(", RAM 32 bit DDR3");
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break;
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2015-10-28 10:46:33 +00:00
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case RAM_DDR3_48:
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printf(", RAM 48 bit DDR3");
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break;
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2015-10-28 10:46:32 +00:00
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default:
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printf(", RAM %d(not supported)", feature_ramconfig);
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break;
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}
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printf(", %d carrier(s) %s", feature_carriers,
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feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s");
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printf(", %d video channel(s)\n", feature_video_channels);
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}
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