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https://github.com/AsahiLinux/u-boot
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91 lines
3 KiB
C
91 lines
3 KiB
C
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/*
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _PSC_DEFS_H_
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#define _PSC_DEFS_H_
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#include <asm/arch/hardware.h>
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/*
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* FILE PURPOSE: Local Power Sleep Controller definitions
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*
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* FILE NAME: psc_defs.h
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*
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* DESCRIPTION: Provides local definitions for the power saver controller
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*
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*/
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/* Register offsets */
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#define PSC_REG_PTCMD 0x120
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#define PSC_REG_PSTAT 0x128
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#define PSC_REG_PDSTAT(x) (0x200 + (4 * (x)))
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#define PSC_REG_PDCTL(x) (0x300 + (4 * (x)))
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#define PSC_REG_MDCFG(x) (0x600 + (4 * (x)))
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#define PSC_REG_MDSTAT(x) (0x800 + (4 * (x)))
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#define PSC_REG_MDCTL(x) (0xa00 + (4 * (x)))
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#define BOOTBITMASK(x, y) ((((((u32)1 << (((u32)x) - ((u32)y) + (u32)1)) - \
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(u32)1)) << ((u32)y)))
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#define BOOT_READ_BITFIELD(z, x, y) (((u32)z) & BOOTBITMASK(x, y)) >> (y)
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#define BOOT_SET_BITFIELD(z, f, x, y) (((u32)z) & ~BOOTBITMASK(x, y)) | \
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((((u32)f) << (y)) & BOOTBITMASK(x, y))
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/* PDCTL */
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#define PSC_REG_PDCTL_SET_NEXT(x, y) BOOT_SET_BITFIELD((x), (y), 0, 0)
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#define PSC_REG_PDCTL_SET_PDMODE(x, y) BOOT_SET_BITFIELD((x), (y), 15, 12)
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/* PDSTAT */
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#define PSC_REG_PDSTAT_GET_STATE(x) BOOT_READ_BITFIELD((x), 4, 0)
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/* MDCFG */
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#define PSC_REG_MDCFG_GET_PD(x) BOOT_READ_BITFIELD((x), 20, 16)
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#define PSC_REG_MDCFG_GET_RESET_ISO(x) BOOT_READ_BITFIELD((x), 14, 14)
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/* MDCTL */
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#define PSC_REG_MDCTL_SET_NEXT(x, y) BOOT_SET_BITFIELD((x), (y), 4, 0)
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#define PSC_REG_MDCTL_SET_LRSTZ(x, y) BOOT_SET_BITFIELD((x), (y), 8, 8)
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#define PSC_REG_MDCTL_GET_LRSTZ(x) BOOT_READ_BITFIELD((x), 8, 8)
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#define PSC_REG_MDCTL_SET_RESET_ISO(x, y) BOOT_SET_BITFIELD((x), (y), \
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12, 12)
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/* MDSTAT */
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#define PSC_REG_MDSTAT_GET_STATUS(x) BOOT_READ_BITFIELD((x), 5, 0)
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#define PSC_REG_MDSTAT_GET_LRSTZ(x) BOOT_READ_BITFIELD((x), 8, 8)
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#define PSC_REG_MDSTAT_GET_LRSTDONE(x) BOOT_READ_BITFIELD((x), 9, 9)
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/* PDCTL states */
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#define PSC_REG_VAL_PDCTL_NEXT_ON 1
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#define PSC_REG_VAL_PDCTL_NEXT_OFF 0
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#define PSC_REG_VAL_PDCTL_PDMODE_SLEEP 0
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/* MDCTL states */
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#define PSC_REG_VAL_MDCTL_NEXT_SWRSTDISABLE 0
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#define PSC_REG_VAL_MDCTL_NEXT_OFF 2
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#define PSC_REG_VAL_MDCTL_NEXT_ON 3
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/* MDSTAT states */
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#define PSC_REG_VAL_MDSTAT_STATE_ON 3
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#define PSC_REG_VAL_MDSTAT_STATE_ENABLE_IN_PROG 0x24
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#define PSC_REG_VAL_MDSTAT_STATE_OFF 2
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#define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG1 0x20
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#define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG2 0x21
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#define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG3 0x22
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/*
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* Timeout limit on checking PTSTAT. This is the number of times the
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* wait function will be called before giving up.
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*/
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#define PSC_PTSTAT_TIMEOUT_LIMIT 100
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u32 psc_get_domain_num(u32 mod_num);
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int psc_enable_module(u32 mod_num);
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int psc_disable_module(u32 mod_num);
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int psc_disable_domain(u32 domain_num);
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#endif /* _PSC_DEFS_H_ */
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