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board: synquacer: Add DeveloperBox 96boards EE support Add the DeveloperBox 96boards EE support. This board is also known as Socionext SynQuacer E-Series. It contians one "SC2A11" SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots, 3 PCIe slots (1 4x port and 2 1x ports which are expanded via PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard MicroATX Form Factor. For more information, see this page; https://www.96boards.org/product/developerbox/ Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-06-04 18:45:10 +09:00
CONFIG_ARM=y
CONFIG_ARCH_SYNQUACER=y
Revert "configs: synquacer: Make U-Boot binary position independent" This reverts commit f7e16bb0c5362c9b01d7e6e96bf6c77fd6b3d89e, since the U-Boot doesn't boot if it is booted directly from SPI-NOR with CONFIG_POSITION_INDEPENDENT=y. Unless fixing this issue, it is better to revert this change. Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-08-19 22:15:25 +09:00
CONFIG_SYS_TEXT_BASE=0x08200000
configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2021-11-01 12:19:22 +00:00
CONFIG_SYS_MALLOC_LEN=0x1000000
Kconfig: Change SYS_MALLOC_F_LEN default to 0x2000 The most commonly used value today is 0x2000 and not 0x400. Rework the Kconfig logic to use this more frequently used value as the default. Cc: Andrew F. Davis <afd@ti.com> Cc: Alex Nemirovsky <alex.nemirovsky@cortina-access.com> Cc: Alexey Brodkin <abrodkin@synopsys.com> Cc: Alison Wang <alison.wang@nxp.com> Cc: Anastasiia Lukianenko <anastasiia_lukianenko@epam.com> Cc: Andes <uboot@andestech.com> Cc: Andre Przywara <andre.przywara@arm.com> Cc: Bharat Gooty <bharat.gooty@broadcom.com> Cc: David Lechner <david@lechnology.com> Cc: Dzmitry Sankouski <dsankouski@gmail.com> Cc: Enric Balletbo i Serra <eballetbo@gmail.com> Cc: Eugeniy Paltsev <paltsev@synopsys.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Gerald Kerma <dreagle@doukki.net> Cc: Gregory CLEMENT <gregory.clement@bootlin.com> Cc: Holger Brunck <holger.brunck@hitachienergy.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Jassi Brar <jaswinder.singh@linaro.org> Cc: Kristian Amlie <kristian.amlie@northern.tech> Cc: Krzysztof Kozlowski <krzk@kernel.org> Cc: Liviu Dudau <liviu.dudau@foss.arm.com> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Lukasz Majewski <lukma@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Masami Hiramatsu <masami.hiramatsu@linaro.org> Cc: Matthias Brugger <mbrugger@suse.com> Cc: Max Filippov <jcmvbkbc@gmail.com> Cc: Michael Walle <michael@walle.cc> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Cc: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Paul Burton <paul.burton@mips.com> Cc: Paul Kocialkowski <contact@paulk.fr> Cc: Priyanka Jain <priyanka.jain@nxp.com> Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com> Cc: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Cc: Sergey Temerkhanov <s.temerkhanov@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Bosch <stefan_b@posteo.net> Cc: Stephan Gerhold <stephan@gerhold.net> Cc: Tetsuyuki Kobayashi <koba@kmckk.co.jp> Cc: Thomas Chou <thomas@wytron.com.tw> Cc: Thomas Fitzsimmons <fitzsim@fitzsim.org> Cc: Thomas Weber <weber@corscience.de> Cc: Tony Dinh <mibodhi@gmail.com> Cc: Trevor Woerner <twoerner@gmail.com> Cc: Vitaly Andrianov <vitalya@ti.com> Cc: Vladimir Zapolskiy <vz@mleia.com> Cc: liuhao <liuhao@phytium.com.cn> Cc: lixinde <lixinde@phytium.com.cn> Cc: shuyiqi <shuyiqi@phytium.com.cn> Cc: weichangzheng <weichangzheng@phytium.com.cn> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Masami Hiramatsu <masami.hiramatsu@linaro.org> Reviewed-by: Tony Dinh <mibodhi@gmail.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Kristian Amlie <kristian.amlie@northern.tech>
2022-04-07 12:33:23 -04:00
CONFIG_SYS_MALLOC_F_LEN=0x400
board: synquacer: Add DeveloperBox 96boards EE support Add the DeveloperBox 96boards EE support. This board is also known as Socionext SynQuacer E-Series. It contians one "SC2A11" SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots, 3 PCIe slots (1 4x port and 2 1x ports which are expanded via PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard MicroATX Form Factor. For more information, see this page; https://www.96boards.org/product/developerbox/ Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-06-04 18:45:10 +09:00
CONFIG_ENV_SIZE=0x30000
CONFIG_ENV_OFFSET=0x300000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="synquacer-sc2a11-developerbox"
configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2022-04-08 13:36:51 -04:00
CONFIG_SYS_LOAD_ADDR=0x80000000
configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-08 07:54:35 -04:00
CONFIG_TARGET_DEVELOPERBOX=y
board: synquacer: Add DeveloperBox 96boards EE support Add the DeveloperBox 96boards EE support. This board is also known as Socionext SynQuacer E-Series. It contians one "SC2A11" SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots, 3 PCIe slots (1 4x port and 2 1x ports which are expanded via PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard MicroATX Form Factor. For more information, see this page; https://www.96boards.org/product/developerbox/ Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-06-04 18:45:10 +09:00
CONFIG_AHCI=y
Migrate CUSTOM_SYS_INIT_SP_ADDR to Kconfig using system-constants.h - Make all users of CUSTOM_SYS_INIT_SP_ADDR reference SYS_INIT_SP_ADDR - Introduce HAS_CUSTOM_SYS_INIT_SP_ADDR to allow for setting the stack pointer directly, otherwise we use the common calculation. - On some platforms that were using the standard calculation but did not set CONFIG_SYS_INIT_RAM_SIZE / CONFIG_SYS_INIT_RAM_ADDR, set them. - On a small number of platforms that were not subtracting GENERATED_GBL_DATA_SIZE do so now via the standard calculation. - CONFIG_SYS_INIT_SP_OFFSET is now widely unused, so remove it from most board config header files. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-05-25 12:16:03 -04:00
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xe0000000
configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-08 07:54:35 -04:00
CONFIG_FIT=y
board: synquacer: Add DeveloperBox 96boards EE support Add the DeveloperBox 96boards EE support. This board is also known as Socionext SynQuacer E-Series. It contians one "SC2A11" SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots, 3 PCIe slots (1 4x port and 2 1x ports which are expanded via PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard MicroATX Form Factor. For more information, see this page; https://www.96boards.org/product/developerbox/ Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-06-04 18:45:10 +09:00
CONFIG_BOOTSTAGE_STASH_SIZE=4096
CONFIG_HUSH_PARSER=y
Convert CONFIG_SYS_MAXARGS to Kconfig This converts the following to Kconfig: CONFIG_SYS_MAXARGS Signed-off-by: Tom Rini <trini@konsulko.com>
2022-05-11 16:21:06 -04:00
CONFIG_SYS_MAXARGS=128
board: synquacer: Add DeveloperBox 96boards EE support Add the DeveloperBox 96boards EE support. This board is also known as Socionext SynQuacer E-Series. It contians one "SC2A11" SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots, 3 PCIe slots (1 4x port and 2 1x ports which are expanded via PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard MicroATX Form Factor. For more information, see this page; https://www.96boards.org/product/developerbox/ Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-06-04 18:45:10 +09:00
CONFIG_CMD_IMLS=y
configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-08 07:54:35 -04:00
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_NVEDIT_EFI=y
board: synquacer: Add DeveloperBox 96boards EE support Add the DeveloperBox 96boards EE support. This board is also known as Socionext SynQuacer E-Series. It contians one "SC2A11" SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots, 3 PCIe slots (1 4x port and 2 1x ports which are expanded via PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard MicroATX Form Factor. For more information, see this page; https://www.96boards.org/product/developerbox/ Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-06-04 18:45:10 +09:00
CONFIG_CMD_NVEDIT_INFO=y
configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-08 07:54:35 -04:00
CONFIG_CMD_DFU=y
board: synquacer: Add DeveloperBox 96boards EE support Add the DeveloperBox 96boards EE support. This board is also known as Socionext SynQuacer E-Series. It contians one "SC2A11" SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots, 3 PCIe slots (1 4x port and 2 1x ports which are expanded via PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard MicroATX Form Factor. For more information, see this page; https://www.96boards.org/product/developerbox/ Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-06-04 18:45:10 +09:00
CONFIG_CMD_DM=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_CMD_PART=y
CONFIG_CMD_PCI=y
CONFIG_CMD_POWEROFF=y
CONFIG_CMD_SATA=y
configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-08 07:54:35 -04:00
CONFIG_CMD_SPI=y
board: synquacer: Add DeveloperBox 96boards EE support Add the DeveloperBox 96boards EE support. This board is also known as Socionext SynQuacer E-Series. It contians one "SC2A11" SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots, 3 PCIe slots (1 4x port and 2 1x ports which are expanded via PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard MicroATX Form Factor. For more information, see this page; https://www.96boards.org/product/developerbox/ Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-06-04 18:45:10 +09:00
CONFIG_CMD_USB=y
configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-08 07:54:35 -04:00
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_RTC=y
board: synquacer: Add DeveloperBox 96boards EE support Add the DeveloperBox 96boards EE support. This board is also known as Socionext SynQuacer E-Series. It contians one "SC2A11" SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots, 3 PCIe slots (1 4x port and 2 1x ports which are expanded via PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard MicroATX Form Factor. For more information, see this page; https://www.96boards.org/product/developerbox/ Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-06-04 18:45:10 +09:00
CONFIG_CMD_FAT=y
configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-08 07:54:35 -04:00
CONFIG_CMD_FS_GENERIC=y
board: synquacer: Add DeveloperBox 96boards EE support Add the DeveloperBox 96boards EE support. This board is also known as Socionext SynQuacer E-Series. It contians one "SC2A11" SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots, 3 PCIe slots (1 4x port and 2 1x ports which are expanded via PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard MicroATX Form Factor. For more information, see this page; https://www.96boards.org/product/developerbox/ Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-06-04 18:45:10 +09:00
CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_LOG=y
configs: Enable EXT4 and ISO partitions for the DeveloperBox Since this box is SystemReady compliant enable ISO_PARTITION which is needed to start some installers (e.g Fedora). While at it enable EXT4 as well which is a common filesystem for targets Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Acked-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2022-04-13 00:16:44 +03:00
CONFIG_ISO_PARTITION=y
board: synquacer: Add DeveloperBox 96boards EE support Add the DeveloperBox 96boards EE support. This board is also known as Socionext SynQuacer E-Series. It contians one "SC2A11" SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots, 3 PCIe slots (1 4x port and 2 1x ports which are expanded via PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard MicroATX Form Factor. For more information, see this page; https://www.96boards.org/product/developerbox/ Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-06-04 18:45:10 +09:00
CONFIG_PARTITION_TYPE_GUID=y
Convert CONFIG_ENV_IS_IN_SPI_FLASH et al to Kconfig This converts the following to Kconfig: CONFIG_ENV_IS_IN_SPI_FLASH CONFIG_ENV_IS_NOWHERE CONFIG_ENV_OFFSET CONFIG_ENV_OVERWRITE CONFIG_ENV_SECT_SIZE CONFIG_SYS_MMC_ENV_DEV CONFIG_SYS_MMC_ENV_PART Signed-off-by: Tom Rini <trini@konsulko.com>
2021-11-07 22:59:38 -05:00
CONFIG_ENV_OVERWRITE=y
board: synquacer: Add DeveloperBox 96boards EE support Add the DeveloperBox 96boards EE support. This board is also known as Socionext SynQuacer E-Series. It contians one "SC2A11" SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots, 3 PCIe slots (1 4x port and 2 1x ports which are expanded via PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard MicroATX Form Factor. For more information, see this page; https://www.96boards.org/product/developerbox/ Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-06-04 18:45:10 +09:00
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_PROT_UDP=y
CONFIG_SCSI_AHCI=y
CONFIG_AHCI_PCI=y
configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-08 07:54:35 -04:00
CONFIG_DFU_TFTP=y
configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2021-11-01 12:19:22 +00:00
CONFIG_DFU_MTD=y
configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-08 07:54:35 -04:00
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
board: synquacer: Add DeveloperBox 96boards EE support Add the DeveloperBox 96boards EE support. This board is also known as Socionext SynQuacer E-Series. It contians one "SC2A11" SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots, 3 PCIe slots (1 4x port and 2 1x ports which are expanded via PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard MicroATX Form Factor. For more information, see this page; https://www.96boards.org/product/developerbox/ Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-06-04 18:45:10 +09:00
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_SYNQUACER=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_F_SDH30=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=31250000
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHYLIB_10G=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y
CONFIG_RGMII=y
CONFIG_MII=y
configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-08 07:54:35 -04:00
CONFIG_SNI_NETSEC=y
nvme: Split out PCI support Apple SoCs have an integrated NVMe controller that isn't connected over a PCIe bus. In preparation for adding support for this NVMe controller, split out the PCI support into its own file. This file is selected through a new CONFIG_NVME_PCI Kconfig option, so do a wholesale replacement of CONFIG_NVME with CONFIG_NVME_PCI. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested on: Macbook Air M1 Tested-by: Simon Glass <sjg@chromium.org>
2022-01-22 20:38:11 +01:00
CONFIG_NVME_PCI=y
board: synquacer: Add DeveloperBox 96boards EE support Add the DeveloperBox 96boards EE support. This board is also known as Socionext SynQuacer E-Series. It contians one "SC2A11" SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots, 3 PCIe slots (1 4x port and 2 1x ports which are expanded via PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard MicroATX Form Factor. For more information, see this page; https://www.96boards.org/product/developerbox/ Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-06-04 18:45:10 +09:00
CONFIG_DM_RTC=y
CONFIG_RTC_PCF8563=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-08 07:54:35 -04:00
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_CONS_INDEX=0
CONFIG_DM_SERIAL=y
CONFIG_PL01X_SERIAL=y
board: synquacer: Add DeveloperBox 96boards EE support Add the DeveloperBox 96boards EE support. This board is also known as Socionext SynQuacer E-Series. It contians one "SC2A11" SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots, 3 PCIe slots (1 4x port and 2 1x ports which are expanded via PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard MicroATX Form Factor. For more information, see this page; https://www.96boards.org/product/developerbox/ Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-06-04 18:45:10 +09:00
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SYNQUACER_SPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_PCI=y
CONFIG_USB_STORAGE=y
configs: Enable EXT4 and ISO partitions for the DeveloperBox Since this box is SystemReady compliant enable ISO_PARTITION which is needed to start some installers (e.g Fedora). While at it enable EXT4 as well which is a common filesystem for targets Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Acked-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2022-04-13 00:16:44 +03:00
CONFIG_FS_EXT4=y
configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-08 07:54:35 -04:00
CONFIG_EFI_SET_TIME=y
configs: synquacer: Enable EFI capsule update support Enable EFI capsule update support. With the EFI capsule update, you can update U-Boot, TF-A and OP-TEE. TF-A and OP-TEE are usually combined as a FIP binary, but if the binary is bigger than 480KB, you have to modify FIP header, split the OP-TEE and stores the OP-TEE binary in the different place. This configuration supports both cases. Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-06-04 18:45:31 +09:00
CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
CONFIG_EFI_CAPSULE_ON_DISK=y
configs: synquacer: Ignore OsIndications on DeveloperBox Since we can not set OsIndications from Runtime Services SetVariables at this moment, it is better to ignore the OsIndications if there is any capsule file in the correct place. Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-07-12 19:36:49 +09:00
CONFIG_EFI_IGNORE_OSINDICATIONS=y
configs: synquacer: Use RAW capsule image instead of FIT Since the recent commit; commit b891ff18f899 ("efi_loader: Force a single FMP instance per hardware store") forces a single FMP instances for a storage, we can not enable both RAW and FIT capsule image support at once. Since RAW capsule image support is simpler than FIT, enable RAW capsule image instead of FIT by default. Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-07-12 19:36:39 +09:00
CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
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